Mitsubishi Denki Kabushiki Kaisha

Other

Renesas Technology Corp.

Renesas Solutions Corporation

Shinji Kawai

Shinichi Kobayashi

Yoshikazu Miyawaki

Masaki Tsukude

Masaaki Mihara

Masashi Wada

Tsukasa Ooishi

Hideto Hidaka

Kazutami Arimoto

Mikio Asakura

Yasuhiko Taito

Masanori Hayashikoshi

Akinori Matsuo

Takeshi Nakayama

Kazuyasu Fujishima

Shigeki Tomishima

Atsushi Ohba

Yoshiki Kawajiri

Shigeru Mori

Tomoshi Futatsuya

Katsuhiro Suma

Shigeru Kikuda

Yoshito Nakaoka

Toshiyuki Ogawa

Tadashi Omae

Kenji Kozakai

Hirofumi Sonoyama

Minoru Ohkawa

Shinichi Ishimoto

Makoto Oi

Jun Eto

A memory mat is provided separately from a memory mat that is a normal memory area, and data therein cannot be read from the outside. In a page buffer, information input from the outside is stored. A comparing circuit compares security information stored in memory mat with information stored in page buffer, and the comparison result is output to the outside as a status. Even when unauthorized copying is performed, information in memory mat is not copied. Therefore, an external apparatus can easily determine whether or not the semiconductor memory is an unauthorized copy by referring to the status.

Semiconductor memory preventing unauthorized copying

A temperature dependency of an internal clock signal generated by an internal clock generating circuit is effectively reduced. A temperature detecting circuit is provided to a variable clock generator for generating the internal clock signal and an oscillating cycle period of the variable clock generator is altered according to a detection signal of the temperature detecting circuit. A cycle of the internal clock signal is altered and a temperature dependency of the internal clock signal is effectively compensated for.

Semiconductor integrated circuit device with internal clock generating circuit

The reliability of a semiconductor integrated circuit device is remarkably improved by minimizing the fluctuations of the detection level of the supply voltage due to the manufacturing process and/or other factors. In the semiconductor integrated circuit device according to the invention, a differential amplifier circuit SA amplifies the differential voltage representing the difference between the reference voltage V generated by a reference voltage generating section and the detection voltage obtained by dividing a supply voltage V by means of resistors and and outputs it as a detection signal K. The reference voltage generating section generates reference voltage V from the base-emitter voltage of a bipolar transistor that is minimally affected by temperature and the manufacturing process so that the fluctuations of the detection level of the supply voltage V can be minimized.

Semiconductor integrated circuit device having reference voltage generating section

A high voltage switch circuit according to the present invention includes PMOS transistors having one conductive terminals receiving a high voltage, NMOS transistors having one conductive terminals receiving a ground voltage, and transistors for voltage control. The transistors for voltage control have their gates supplied with gate control signals of which potential change in accordance with the level of the high voltage. Thus, a high voltage switch circuit which can normally operate independent of the voltage level can be provided.

High voltage switch circuit having transistors and semiconductor memory device provided with the same

A voltage generation portion includes a voltage amplifier circuit, receiving a boosted potential VPP generated by a charge pump circuit to output an output potential Vout equal to a standard potential VIN. Output potentials Vout are distributed as voltages for rewriting and erasing on a flash memory via distributor. The output potential Vout can be changed faster than the boosted potential VPP generated by the charge pump circuit does.

Nonvolatile semiconductor memory device capable of high speed generation of rewrite voltage

A memory cell array is divided into a plurality of memory cell blocks each collectively subjected to an erasing operation as a unit. A P well regions for memory cell transistors and an N well region for electrically separating the P well regions are provided. Select transistors are formed in the same P well region as the memory cell transistor connected to the corresponding sub bit line of P well regions.

Nonvolatile semiconductor memory device capable of reducing memory array area

Following latching of a word line select signal by a latch circuit, a transfer gate is turned off. When a word line is selected, the voltage applied to the latch circuit is shifted to a desired level to apply a desired voltage to the word line from a word line driver. As a result, a predecode signal is applied to a small size buffering circuit to be transmitted to the word line driver at a potential level between Vcc-GND. Therefore, the parasitic capacitance accompanying a predecode signal is reduced.

Semiconductor memory device that can realize high speed data read out

The inventive DINOR flash memory includes a plurality of blocks, a spare block and a spare word line block, which are formed on a plurality of electrically isolated P-type wells. When a word line-to-well short-circuit takes place in a certain block and another block is selected, the block causing the word line-to-well short-circuit is brought into a non-selected state. Thus, no leakage takes place in the block causing the word line-to-well short-circuit, to exert no bad influence on the selected block.

Nonvolatile semiconductor memory device having a plurality of blocks

In a confirmation operation of write data after writing data into a memory cell transistor (a verify operation), a verify potential generation circuit supplies a verify potential VPVRFY to the control gate of a memory transistor. Verify potential VPVRFY is determined depending upon the resistance ratio of variable resistors and a value of a constant current supplied from a constant current source circuit. According to reduction of a power supply potential, potential VPVRFY is decreased. The conductance of a memory cell transistor is adjusted according to variation in a detection sensitivity of a sense amplifier according to variation in the power supply potential, whereby the cell threshold value after a write operation takes a constant value.

Non-volatile semiconductor memory device having large margin of readout

A source line of a memory array included in a flash memory is set to a 3V potential by a source line circuit, a power supply voltage of 6V is applied to a sense amplifier, and 3V is applied as the ground potential. After the setting of such potential conditions, reading of the memory array is performed. When current flows to the memory cells as a result of reading, it means that the memory cell has been erased. If the current does not flows through the memory cell, erasure pulse is applied again and every memory cell is verified.

Nonvolatile semiconductor memory device and method of erasing stored

A substrate potential generating circuit can generate a lower substrate potential. The substrate potential generating circuit includes a clock signal generating circuit and first and second charge pump circuits. The first charge pump circuit including a p-channel MOS transistor having its source electrode connected to the semiconductor substrate applies a first negative potential to the drain electrode by capacitive coupling of a capacitor. The second charge pump circuit including first and second sub-charge pump circuit applies a third negative potential to the gate electrode when the first negative potential is applied to the drain electrode, and thereafter provides a second potential by lowering the third potential. As a result, the p-channel MOS transistor is turned on until a substrate potential is brought into a potential equal to the first potential applied to the drain electrode, lowering the substrate potential to the first potential.

Substrate potential generating circuit generating substrate potential of

Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

Column selecting circuit in semiconductor memory device

An n channel driver circuit comprised of an N channel MOS transistor is provided in parallel to a driver circuit comprised of a P channel MOS transistor. Normally, n channel driver circuit supplies an internal supply voltage, to activate driver circuit only at the time of current peak. Thus, an insufficient capability of n.sup.- channel driver circuit to supply current is supplemented.

Semiconductor device incorporating internal voltage down converting

A semiconductor integrated circuit device comprising an internal reset circuit generating one shot pulse for resetting an internal circuit upon a power on. In the internal reset circuit, inputted to a two-input NOR gate are an output potential of an inverter inverting a first node coupled to a power supply through a capacitor, and an internal clock signal which level inverts at a predetermined timing after rising to a 'H' level upon the power on. Then, the output of the NOR gate is applied to a second node in an internal circuit to be reset. The internal reset circuit outputs one shot pulses synchronizing with the first fall of the internal clock signal after the power on irrespective of a potential change rate of the first node after the power on. The first node is set to more easily attain a 'H' level than the second node to be reset to a 'L' level at the power on by adjusting characteristics of circuit elements connected to the first node and those of circuit elements connected to the second node. As a result, the second node is set to be without fail at a 'L' level requiring no resetting when the inverted potential of the first node has a value allowing a generation of one shot pulses at the NOR gate, thereby preventing malfunction of the internal circuit due to erroneous resetting.

Power on reset circuit for semiconductor integrated circuit device

A semicondcutor memory device includes an array of a plurality of memory cells arranged in a matrix manner, and a row or column decoder responsive to an external address signal for generating a row or column selecting signal. The memory cell array comprises (n+1) rows or columns. The row or column decoder comprises n output nodes. Transmission gates are provided between the decoder output node and row lines or column selecting lines for connecting each output node and each row line or column selecting line. The transmission gates are formed of a pair of CMOS transmission gates, whereby one output node is connected to two adjacent row lines or column selecting lines. This memory device further includes a circuit defining the connection manner of the transmission gate. This defining circuit turns one pair of CMOS transmission gates ON and OFF complementally. When there is a defective memory cell, the decoder output nodes are grouped into a first group including the output node corresponding to the faulty row or column having the defective memory cell, and a second group formed of the remaining output nodes. The defining circuit applies control signals to the CMOS transmission gates so that the ON/OFF states of the CMOS transmission gate pair related to the first group of output nodes and the CMOS transmission gate pair related to the second group of output node differ. The memory device further includes switching devices provided corresponding to each row line or column selecting line, responsive to the control signal from the defining cirucit to be turned on/off. This switching device connects only the faulty row line or the faulty column selecting line to the reference potential fixedly.

Growing community of inventors

Hyogo, Japan

Shinji Kawai