Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Shinji Fujii

Kazuhiko Kasai

Kenji Matsuo

Tadahiro Kuroda

Yasukazu Noine

Masahiro Kimura

Kouichirou Inoue

Toshikazu Sei

Muneaki Maeno

Toshiki Morimoto

Yukinori Uchino

Yoshiaki Hashiba

Munenori Sakai

Ikuo Tsuchiya

Ayako Hirata

Toshiyuki Fukunaga

Naoto Higuchi

Nobuhiko Kurata

Taisei Suzuki

A protective circuit includes a first line, a second line, and a signal line. A first and second diode are connected in series between the first and second lines. A resistor and a capacitor are connected between the first and second lines. A first inverter, a second inverter, a third inverter are connected in series between a node between the resistor and capacitor and a gate of a first transistor. A third diode is connected between the first and second lines. The first transistor is connected between the first and second lines. A second transistor is connected between the first line and a protected circuit. A gate of the second transistor is connected to the output of the first inverter. A third transistor is connected between the second line and the protected circuit. A gate of the third transistor is connected to output of the second inverter.

Protective circuit

A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.

Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy

Semiconductor devices whose current characteristics can be prevented from varying even if a phase shift mask is used for patterning gate electrodes of MISFETs, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, there is provided a semiconductor device comprising a first transistor including a first gate electrode provided above a semiconductor substrate, and a first source and a first drain provided in the semiconductor substrate, a second transistor arranged to be adjacent to the first transistor, and including a second gate electrode provided above the semiconductor substrate in parallel with the first gate electrode, and a second source and a second drain provided in the semiconductor substrate, and a third gate electrode provided between the first transistor and the second transistor and in parallel with the first and second gate electrodes.

Semiconductor device and manufacturing method thereof

A plurality of terminals is formed in a basic cell. One terminal has first to fifth patterns. The first and second patterns are arranged to be spaced from each other. The third and fourth patterns are arranged to be spaced from each other, and are arranged so as to be adjacent to the first and second patterns. The fifth pattern is arranged between the first and second grid lines to interconnect the first to fourth patterns. A dimension of the fifth pattern in a direction of extension of a plurality of grid lines is set to be smaller than a dimension obtained by adding dimensions of the first and second patterns in the direction of extension of the grid lines to an interval of the both patterns, and a dimension obtained by adding dimensions of the third and fourth patterns to an interval of the both patterns.

Master slice type semiconductor integrated circuit device

A semiconductor device containing a multi-layered wiring structure formed on a semiconductor substrate, the structure including at least two wiring layers formed in an interlayer insulation layer, and each of the wiring layers including a metal wiring made of one of Cu and a Cu alloy, wherein the multi-layered wiring structure comprises a lower wiring layer formed under the interlayer insulation layer, a via buried in the interlayer insulation layer to connect an upper wiring layer and the lower wiring layer, and a dummy via buried in the interlayer insulation layer, the dummy via being not connected to the upper wiring layer.

Semiconductor device

A semiconductor device includes a plurality of circuits, provided on a semiconductor substrate, each having a plurality of wiring layers. The plurality of circuits are designed using a common design core to which a plurality of wiring data are allocated.

Semiconductor device provided using wiring data of common design core

A differential current source circuit includes three P-channel MOSFETs and two N-channel MOSFETs. Each source of first and second P-channel MOSFETs is connected to a power supply, and a bias voltage is applied to each gate of the MOSFETs. A current path of the first N-channel MOSFET is connected between a drain of the first P-channel MOSFET and a ground. A current path of the third P-channel MOSFET is connected between a drain of the second P-channel MOSFET and a current output terminal. A gate of the third P-channel MOSFET is connected to the drain of the first P-channel MOSFET. One end of a current path of the second N-channel MOSFET is connected to a connecting point of the first P-channel and first N-channel MOSFETs, and the other end is connected to a connecting point of the second P-channel and third P-channel MOSFETs. A digital signal is applied to a gate of the second N-channel MOSFET.

Differential current source circuit in DAC of current driving type

The output terminal of an ECL circuit is directly connected to the input terminal of a CMOS output circuit. The CMOS output circuit has a transistor which sets the threshold voltage of the CMOS output circuit nearly midway between ECL logic levels. A first reference voltage generating circuit has substantially the same arrangement as the CMOS output circuit and outputs a potential midway between CMOS logic levels as a first reference voltage Vref1. The first reference voltage Vref1 is made variable. A second reference voltage generating circuit has substantially the same arrangement as the ECL circuit and outputs a potential which is midway between the ECL logic levels as a second reference voltage Vref2. A comparator makes a comparison between the first and second reference voltages Vref1 and Vref2 and controls the first reference voltage generating circuit and the CMOS output circuit so that the first and second reference voltages Vref1 and Vref2 may become equal to each other.

Level translator capable of high speed operation

The gate of a first P-channel transistor of a first comparator is supplied with an input signal, and the gate of a second P-channel transistor of the first comparator is supplied with a reference voltage. An output terminal of the first comparator is connected to an output circuit and the gates of first and second P-channel transistors of a second comparator are supplied with the reference voltage. The second comparator outputs a voltage equal to a stand-by time output voltage of the first comparator and the output voltage from the second comparator is supplied to the non-inversion input terminal of a third comparator which is connected to a voltage generating circuit. The voltage generating circuit has substantially the same dimension ratio as the output circuit and generates a voltage equal to the threshold voltage of the output circuit. A third comparator controls the first P-channel transistors of the first and second comparators in accordance with a difference voltage between the output voltage of the second comparator and the output voltage of the voltage generating circuit to thereby automatically set a stand-by time output voltage of the first comparator at a value close to the threshold of the output circuit.

Semiconductor integrated circuit capable of compensating errors in

This invention discloses a switching constant current source circuit including a first current path for supplying a constant current, a first MOS transistor, one end of a current path of which is connected to the first current path, the other end of the current path of which is connected to a second current path, and a gate of which is applied with a digital signal corresponding to a logical amplitude, a second MOS transistor, one end of a current path of which is connected to the first current path, the other end of the current path of which is connected to a third current path, and which performs a switching operation complementary with the first MOS transistor, and level conversion means for fetching a change in voltage in the first current path caused by a change in current flowing through the first current path according to an operation of the first MOS transistor in response to the digital signal, and alternately applying a first level for disabling the second MOS transistor, which operates complementarily with the first MOS transistor, and a second level for enabling the second MOS transistor to output a predetermined current.

Switching constant current source circuit

A retriggerable multivibrator is disclosed which comprises a first delay circuit connected for delaying an input signal a predetermined time, a second delay circuit connected to receive an output of the first delay circuit and having a enable or disable function, a flip-flop circuit connected to be set or reset in accordance with an input signal and output signal from the second delay circuit, and a control circuit for detecting a subsequent input signal within a predetermined delay time to enable or disable the second delay circuit.

Growing community of inventors

Yokohama, Japan

Shinji Fujii