Fujitsu Corporation

Shinji Emori

Yoshio Watanabe

Masaya Tamamura

Hiroshi Nishimoto

Masahiro Sugimoto

Tadashi Okiyama

Akira Miyauchi

Hiroo Kitasagami

Haruo Tamada

Isao Shimotsuhama

Hikotaro Masunaga

A controllable delay logic circuit includes a differential circuit having first and second transistors, a first load coupled between a first power supply line and the collector of the first transistor, a second load coupled between the first power supply line and the collector of the second transistor, and a constant-current source connected between a second power supply line and the emitters of the first and second transistors. The controllable delay logic circuit also includes a first power source, a first current path circuit having a first resistor and selectively allowing a first current to pass through the first transistor from the first power source via the first resistor, and a second current path circuit having a second resistor and selectively allowing a second current to pass through the second transistor from the first power source via the second resistor.

Controllable delay logic circuit for providing variable delay time

A signal generator having a Johnson counter including a plurality of flip-flops having CLOCK inputs to which a clock signal is inputted; a logic gate to which the clock signal and Q outputs of the flip-flops are inputted, the logic gate being constructed such that the clock signal is passed therethrough each time 2n clock pulses of the clock signal occur and that the logic gate outputs its output as a first signal, n representing the number of the flip-flops of the Johnson counter; and delay means for delaying the clock signal by a time corresponding to an input-output delayed time of the logic gate and for outputting the delayed clock signal as a second signal.

Signal generator for generating a delayed clock signal

A master-slave flip-flop circuit is made up of a master part which holds a data signal responsive to a clock signal and outputs the held data signal in the form of complementary output signals, and a slave part which holds the complementary output signals responsive to the clock signal and outputs at least one of the held complementary output signals. The complementary output signals of the master part have a logic amplitude which is smaller than a logic amplitude of the output signal of the slave part to ensure correct operation even when the data signal and the clock signal have high frequencies.

Master-slave flip-flop circuit

A gate array device forms an arbitray logic circuit depending on interconnections formed thereon, and comprises a semiconductor chip having an approximate rectangular shape, an input terminal region including a plurality of input terminals formed at a peripheral portion of the semiconductor chip, an output terminal region including a plurality of output terminals formed at a peripheral portion of the semiconductor chip, and a macro cell region including a plurality of macro cells formed at a central portion of the semiconductor chip. The macro cells include first macro cells and second macro cells, where each of the first macro cells include a minimum number of elements for forming a master part of a master-slave flip-flop circuit and each of the second macro cells include at least a minimum number of elements for forming a slave part of the master-slave flip-flop circuit. The first macro cells and the second macro cells make macro cell pairs and are regularly arranged within the macro cell region.

Gate array device having macro cells for forming master and slave cells

An ECL transistor pair is connected in parallel with a third transistor. A complementary signal is applied to the transistor pair. A high level of a signal that is applied to the third transistor is effectively higher than a high level of the input to the pair of transistors; and a low level of the signal applied to the third transistor is effectively lower than the high level of the input to the pair of transistors. The low level input to the third transistor enables the ECL circuit to output the complementary input signal and assures high speed ECL operation. The high level of the input to the third transistor disables the ECL circuit from outputting the complementary input signal.

Referenceless ECL logic circuit

Semiconductor device

An integrated circuit device including: at least one semiconductor chip (3) having a plurality of circuit elements; a package (21 to 24) enclosing the semiconductor chip with a hermetic seal; and a strip line unit (15-2, 11-1b, 11-2, 20 and 23:15-1, 11-1, 11-2, 11-3, 12-1 and 20) for connecting the circuit elements in the semiconductor chip to circuit outside of the package. The stripline unit having a microstrip line structure and a triplate strip line structure serial-connected to the microstrip line structure and connecting the outside circuits. The triplate strip line structure has a characteristic impedance equal to that of the microstrip line structure so that the strip line unit satisfies the required impedance matching. A center of the conductive layer strip line of the triplate strip line structure has a smaller width than that of a microstrip line of the microstrip line structure to have a predetermined impedance so that the triplate strip line structure has a same characteristic impedance as that of the microstrip line structure.

Integrated circuit device having strip line structure therein

An integrated circuit device including a stacked layer unit having a plurality of stacked layers each having an insulation layer and at least one conductive layer strip formed on a surface of the insulation layer, and at least one chip mounted on the top of the insulation layer and having a plurality of circuit elements. The IC device also includes at least one first conductive member formed in the stacked layer unit, having a low inductance for first signals applied thereto and operatively connecting the first signals to be transferred between the circuit elements. The IC device further includes at least one second conductive member formed in the stacked layer unit, having a higher inductance for the first signals than that of the first conductive member and operatively connecting second signals to be transferred between the circuit elements the stacked layer unit, the chip, and the first and second conductive members are enclosed by a package and sealed with a hermetic seal.

Integrated circuit device having stacked conductive layers connecting

A semiconductor device includes a diffusion layer in the semiconductor substrate thereof; and an insulation layer is formed on the semiconductor substrate and is provided with a contact window therein, so as to electrically connect a conductive metal layer with the diffusion layer composed of Si atoms as a base material. A Si atom supplier is formed close to the contact window at the area where the Si atoms diffuse into the conductive metal layer. Preferably, the Si atom supplier comprises a dummy contact window similar to the above-mentioned real contact window.

Semiconductor device having electric contacts with precise resistance

A driver for transmitting a digital differential signal along a transmission line during a packet time and not during an idle time while maintaining a constant common voltage between the transmission line and ground throughout the packet and idle time periods. A driving circuit and its drive controller in the driver and respectively formed from paired matched transistors which function as on-off switching circuits and have a common emitter load acting as a constant current source. A collector of a first transistor in the drive controller is connected to the common emitter of the driving circuit and a collector of a second transistor in the drive controller is respectively connected to the collectors of the pair of transistors of the driving circuit through respective matched diodes. During the idle time, the driving circuit is cut off by the first transistor being cut off, and the second transistor carries collector current, which is separated into halves, through respective matched collector resistors in the driving circuit and the matched diodes. The voltage on each collector in the pair of transistors in the driving circuit becomes the mean value of a high and a low voltage levels produced during the packet time. The constant common voltage can be obtained from this mean voltage by using emitter followers. Matched transistors can be used instead of the matched diodes.

Driver for differential signal transmission

An emitter-coupled logic (ECL) circuit having a pull-down resistor and including a breakdown protecting structure. Such breakdown occurs in an input transistor for receiving input data when an excess reverse voltage is applied across the emitter and base of the input transistor. The breakdown protection structure preferably includes a constant-voltage regulating device which can always clamp the level of a reference voltage V.sub.BB to a suitable level higher than a low voltage V.sub.EE of a power source by the value of a constant voltage. The reference voltage V.sub.BB is usually applied to the base of another transistor which should be coupled, at respective emitters, with the input transistor by the representative emitters.

Emitter-coupled logic circuit

A semiconductor device provided with signal lines which connect a chip, provided at a top portion of a package, with external terminals provided at a bottom portion of the package. The signal lines have portions formed along side surfaces of the package. Ground surfaces are formed at predetermined distances on two sides of the high-speed signal lines. A coplanar waveguide is formed by the high-speed signal lines and the ground surfaces, so the impedance of vertical portions of the high-speed signal lines is matched to the circuits connected thereto.

A variable-threshold-type differential signal receiver comprises a differential amplifier for comparing differential voltages of differential input signals with a predetermined threshold voltage so as to provide logical output signals. It further comprises an emitter follower and an impedance means, the output of the emitter follower being superimposed through the impedance means on one of the differential input signals, whereby the predetermined threshold voltage is variably controlled by controlling the input voltage of the first emitter follower.

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Urawa, Japan

Shinji Emori