Micron Technology Incorporated

Shinji Bessho

Takuya Nakanishi

Toru Ishikawa

Takumi Nasu

Kiyotake Sakurai

Koichiro Ito

An apparatus includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit which is configured to activate first and second internal signals in a time-division manner in response to a first external command A first number of the word lines arc selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal. The second number is smaller than the first number.

Semiconductor device performing row hammer refresh operation

Disclosed herein is an apparatus that includes a command shifter configured to receive a command pulse and generate a plurality of first command shifted pulses in parallel, wherein each of the plurality of first command shifted pulses has the same width as the command pulse and the plurality of first command shifted pulses have different phases from each other, and a command filter configured to determine if a plurality of second command shifted pulses are generated correspondingly to the plurality of first command shifted pulses or not generated responsive to pulse overlapping among at least ones of the plurality of first command shifted pulses.

Command filter filtering command having predetermined pulse width

Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.

Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-di vision manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.

A system for refresh operations in semiconductor memories, and an apparatus and method therefore, are described. The system includes, for example, memory cells in memory banks that are refreshed during a self-refresh operation or an auto refresh operation. The self-refresh operation includes a different number of refresh activations than the auto refresh operation. The system further includes a row control circuit configured to refresh the memory cells in the memory banks based on refresh control signals received from a refresh control circuit, the refresh control signals provided by the refresh control circuit based on internal control signals received by the refresh control circuit from a command control circuit. The auto refresh operation includes a per bank refresh operation configured to refresh a corresponding memory bank or an all-bank refresh operation configured to refresh all memory banks.

Apparatuses and methods for refresh operations in semiconductor memories

A system for refresh operations including multiple refresh activations, and a method and an apparatus therefore, are described. The system includes, for example, a memory array; a command address input circuit configured to provide a command for a per bank refresh operation or an all-bank refresh operation, a command control circuit configured to receive the command, and provide first and second internal control signals; a refresh control circuit configured to provide a first refresh control signal; and a row control circuit configured to provide a second refresh control signal. The provided first internal control signal is based on the provided command. For the per bank refresh operation, the provided second internal control signal is based on the second refresh control signal, and, for the all-bank refresh operation, the provided second internal control signal is based on the first internal control signal delayed by the command control circuit.

Apparatuses and methods for refresh operations including multiple refresh activations

Embodiments of the disclosure are drawn to apparatuses and methods for generating a refresh address locally at a memory bank. The memory bank may include or be associated with a bank logic circuit that latches an initial refresh address from a global row address bus for a first pump of a refresh operation. The bank logic circuit then updates the latched refresh address received to generate a new refresh address for a second pump of the refresh operation. A memory device may include multiple memory banks that share the global row address bus.

Apparatuses and methods for multi-bank and multi-pump refresh operations

A memory architecture for an array of memory cells having a plurality of sections of memory and a plurality of regions disposed between the plurality of sections of memory. Each section of memory having a plurality of memory cells arranged in rows and columns of memory and a plurality of sense amplifiers located in each of the plurality of regions. The sense amplifiers coupled to a respective column of memory. A plurality of column select lines are located in each of the plurality of regions with each column select line coupled to a group of column select switches associated with a section of memory to activate the respective column select switches.

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Hachioji, Japan

Shinji Bessho