Sony Semiconductor Solutions Corporation

Sony Group Corporation

Shinichirou Etou

Yusuke Ikeda

Kazutoshi Tomita

Yosuke Ueno

Yasufumi Hino

Atsumi Niwa

Daisuke Nakagawa

Tetsuya Fujiwara

Atsushi Suzuki

Shun Kaizu

Tsutomu Imoto

Takuya Maruyama

Eiji Hirata

Kenichi Takamiya

Hiroshi Yuasa

Daisuke Hirono

Naoya Arisaka

Atsushi Muto

Yasutaka Kimura

Takahiro Akahane

Taiki Iguchi

Naoto Nagaki

Masafumi Yamashita

Ren Hiyoshi

Takeshi Oyakawa

The range-finding apparatus includes a light source, an optical receiver, a setting unit, a detector, and a calculation unit. The light source projects light with a first irradiation pattern in a first period and projects light with a second irradiation pattern in a second period. The optical receiver receives light to output a pixel signal. The setting unit sets a reference signal based on the pixel signal in the first period. The detector detects whether or not the pixel signal varies from the reference signal by a first value or more in the second period and outputs a first detection signal indicative of a result obtained by the detection. The calculation unit calculates a distance to a to-be-measured object using the first detection signal.

Range-finding apparatus and range-finding method

Solid state imaging devices and electronic devices are disclosed. In one example, an imaging device includes photoelectric conversion sections arranged on a first chip and at least a part of each of detection circuits, an arbiter, and a signal processing circuit arranged on a second chip stacked on the first chip. A first region in the first chip in which the photoelectric conversion sections is arrayed and a second region in the second chip in which at least a part of each of the detection circuits is arrayed are at least partially superimposed in a stacking direction, and a logic circuit including the arbiter and the signal processing circuit is arranged in a third region at least partially adjacent to the second region in the second chip.

Solid imaging device and electronic device

Suppressing a dead period at the time of mode switching. A solid-state imaging device includes: a plurality of pixels () that each outputs a luminance change of incident light; and a detection circuit () that outputs an event signal based on the luminance change output from each of the pixels, in which each of the pixels includes: a photoelectric conversion element () that generates a charge according to an incident light amount; a logarithmic conversion circuit () that is connected to the photoelectric conversion element and converts a photocurrent flowing out of the photoelectric conversion element into a voltage signal corresponding to a logarithmic value of the photocurrent; and a first transistor () having a drain connected to a sense node of the logarithmic conversion circuit.

Solid-state imaging device with transistor drain connected to sense node of logarithmic conversion circuit

Solid-state imaging devices are disclosed. In one example, a solid-state imaging device includes a conversion circuit connected to a vertical signal line of a pixel array, a voltage generation circuit that outputs a predetermined voltage, and a reference voltage generation circuit that receives the predetermined voltage and outputs a reference voltage. The reference voltage generation circuit includes an operational amplifier that amplifies the predetermined voltage and outputs the reference voltage, a capacitive element having one end connected to an input of the operational amplifier that is different from an input that receives the predetermined voltage, a first switching circuit that connects the other end of the capacitive element to either the predetermined voltage output from the voltage generation circuit or a feedback loop of the operational amplifier, and a second switching circuit that selectively connects the one end of the capacitive element to the feedback loop of the operational amplifier.

Solid-state imaging device and electronic apparatus

It is intended to improve reading speed of pixel signals in a solid-state imaging element provided with an ADC. A plurality of pixels are arrayed in a pixel block. A drive circuit drives the pixel block to output a plurality of pixel signals at the same time. A comparator successively selects the plurality of pixel signals and compares the selected pixel signals and a predetermined reference signal. A control section generates a control signal for updating the predetermined reference signal on the basis of comparison results of the comparator. A reference signal update section updates the predetermined reference signal according to the control signal.

Solid-state imaging element, imaging apparatus, and control method of solid-state imaging element with improved reading speed of pixel signals

A solid state imaging element according to an embodiment includes: a converter () that converts an analog pixel signal read out from a pixel into a bit value, successively for each of a plurality of bits, on the basis of a threshold voltage set according to a conversion history of the bit converted before a target bit; a plurality of voltage generation units (and) that each generate a plurality of reference voltages; and a setting unit () that sets the threshold voltage using the reference voltage selected from the reference voltages generated by each of the voltage generation units on the basis of a conversion result.

Solid state imaging element and electronic apparatus

A solid-state imaging device configured to suppress fixed pattern noise having column correlation and/or lateral correlation from being generated in images is disclosed. In one example, a solid-state imaging device includes unit pixels arranged in row and column directions, vertical signal lines respectively connected to at least one of the unit pixels arranged in the column direction, first converters connected to the respective vertical signal lines and configured to convert an analog pixel signal into a digital pixel signal in reading each unit pixel arranged in the row direction, an initialization voltage generator that outputs an initialization voltage for initializing the unit pixels or input nodes of the first converters, and an initialization voltage line that connects the initialization voltage generator and the first converters. The initialization voltage generator changes the initialization voltage that is output for each row and/or column to be processed by the first converters.

Solid-state imaging device

An imaging element according to a first aspect includes: a successive approximation resistor type analog-digital converter that converts an analog signal output from a pixel including a photoelectric conversion part into a digital signal, in which the successive approximation resistor type analog-digital converter has a preamplifier having a band limiting function. An imaging element according to a second aspect includes a DAC in which the successive approximation resistor type analog-digital converter uses a capacitance element to convert a digital value after AD conversion to an analog value, and sets the analog value to a comparison reference for comparison with an analog input voltage. Then, the DAC includes one of lower-bit capacitance elements including a plurality of capacitance elements, and after performing AD conversion for all bits, each of the plurality of capacitance elements is selectively applied with at least a first reference voltage to a fourth reference voltage, so that re-AD conversion is performed for lower bits.

Imaging element and electronic device

A solid state imaging element () includes: a successive approximation type analog-digital conversion circuit () converting an analog pixel signal received from a pixel of a pixel array portion () to a digital code; and a first noise detection circuit (-) connected to a DAC (Digital to Analog Converter) output node inside the successive approximation type analog-digital conversion circuit () and detecting power noise supplied to the pixel of the pixel array portion () to output a detection result to the DAC.

Solid state imaging element, electronic apparatus, and power noise correction method

An A/D converter and electronic equipment are disclosed. In one example, an A/D converter includes a comparator circuit and a first transistor. The comparator circuit compares a threshold voltage (V) to a pixel signal (S). The first transistor has a control terminal and forms a clamp circuit, and receives an input of a result of the comparison. When the clamp circuit is turned on (closed), the first transistor equalizes currents flowing to a first predetermined position and a second predetermined position or equalizes voltages at the first predetermined position and the second predetermined position, the first predetermined position and the second predetermined position being connected to each other at the time of clamping. This makes it possible to suppress occurrence of streaking in a case where an excessive input is applied to a pixel signal line side.

A/D converter and electronic equipment

Power consumption of a time-to-digital converter (TDC) used in a phase locked loop (ADPLL) is suppressed. The time-to-digital converter includes an analog-to-digital converter and a current source circuit. The analog-to-digital converter includes a predetermined charge capacitor. The current source circuit supplies a charge current that charges the charge capacitor of the analog-to-digital converter with a charge. The charge current supplied by the current source circuit is supplied so that a charge voltage at the time of charging the charge capacitor of the analog-to-digital converter with the charge current has a constant gradient with respect to a charge time.

Time-to-digital converter and phase locked loop

A first successive approximation register analog-to-digital converter according an embodiment of the present disclosure includes an N-bit (N represents an integer greater than or equal to 5) capacitive digital-to-analog converter including a plurality of capacitive elements. A plurality of first capacitive elements of the plurality of capacitive elements is capacitive elements that have total capacity corresponding to total capacity of a plurality of the capacitive elements corresponding to a whole or a portion of first to (N&#x2212;1)-th bits, and do not correspond to the first to (N&#x2212;1)-th bits.

Successive approximation register analog-to-digital converter

The present technology relates to a phase-locked loop that allows a reduction in power consumption. A SAR-ADC that includes two capacitors and outputs a result of comparison between voltages generated from the two capacitors, a current source that charges the two capacitors with current, a first switch that is disposed between one of the two capacitors and the current source and is provided with a phase difference between a first clock of a reference frequency and a second clock having a higher frequency than the first clock, and a second switch that is disposed between another of the two capacitors and the current source and is provided with the second clock are included. The present disclosure can be applied, for example, to a wireless communication device.

Phase-locked loop

The present invention aims to reduce power consumption in an ADC that performs AD conversion of a single-ended signal. A pair of sampling capacitors samples the single-ended signal. After the single-ended signal has been sampled, the connection control unit performs positive-side connection control of connecting both ends of one of the pair of sampling capacitors across a positive-side signal line and a predetermined ground potential and performs negative-side connection control of connecting both ends of the other of the pair of sampling capacitors across a negative-side signal line and the predetermined ground potential. A conversion unit converts a differential signals from the positive-side signal line and the negative-side signal line that have respectively undergone the positive-side connection control and the negative-side connection control into a digital signal.

Growing community of inventors

Kanagawa, Japan

Shinichirou Etou