Renesas Electronics Corporation

Renesas Technology Corp.

Shinichiro Yanagi

Tetsuya Nitta

Katsumi Morii

Yoshitaka Otsu

Kazuma Onishi

Hiroshi Kimura

Fumitoshi Yamamoto

Yasunori Yamashita

A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

Semiconductor device and method for manufacturing the same

In the interior of a semiconductor substrate having a main surface, a first pepitaxial region is formed, a second pepitaxial region is formed on the main surface side, and an n-type drift region and a p-type body region are formed on the main surface side. An nburied region is formed between the first pepitaxial region and the second pepitaxial region in order to electrically isolate the regions. A pburied region having a p-type impurity concentration higher than that of the second pepitaxial region is formed between the nburied region and the second pepitaxial region. The pburied region is located at least immediately under the junction between the n-type drift region and the p-type body region so as to avoid a site immediately under a drain region which is in contact with the n-type drift region.

Semiconductor device

There is provided a semiconductor device in which the degradation of electric characteristics can be inhibited. A semiconductor substrate has a main surface, and a trench in the main surface. A buried insulating film is buried in the trench. The trench has one wall surface and the other wall surface which oppose each other. A gate electrode layer is located over at least the buried insulating film. The trench has angular portions which are located between the main surface of at least either one of the one wall surface and the other wall and a bottom portion of the trench.

Semiconductor device and method of manufacturing the same

The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an ntype semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.

Growing community of inventors

Kanagawa, Japan

Shinichiro Yanagi