Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Hitachi Information Control Systems, Inc.

Hitachi Engineering Ltd

Shinichiro Yamaguchi

Yoshihiro Miyazaki

Soichi Takaya

Tadaaki Bandoh

Hidekazu Matsumoto

Hirokazu Hirayama

Kenji Hirose

Tetsuaki Nakamikawa

Shin Kokura

Hiroaki Nakanishi

Naoto Miyazaki

Koji Matsuda

Kenichi Kurosawa

Jushi Ide

Atsuhiko Nishikawa

Masayuki Tanji

Takayuki Morioka

Yuuichiro Morita

Yukio Kawamoto

Nobuo Akeura

Akira Yamagiwa

Takuji Hamada

Kenji Kashiwagi

Hiroaki Fukumaru

Masao Inoue

Yoshinori Ohkura

Shunji Inada

Takao Kobayashi

Sako Ishikawa

Hiroshi Tomizawa

Hiroshi Ohguro

Satoru Kayukawa

Masataka Hiramatsu

Kazuhiro Hyuga

Hiroshi Oguro

Kenzi Hirose

Morioka Takayuki

A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which effect the same operation in synchronism with each other. Each of the processing units includes a copy processor register for designating a processor to read out contents of a memory unit, a memory copy control unit for transferring copies of the stored contents of the memory unit and data to be written into the memory unit in the same order as that of accesses to the memory unit of the other processing unit, a copy mode flag indicating that memory copy processing for making the stored contents of the memory unit of the self system and stored contents of the memory unit of the other processing unit coincide with each other is proceeding, and a copy task flag indicating that the processor is reading out, during memory copying processing, the stored contents of the memory unit.

Multiplexed computer system

A fault-tolerant computer system, which prevents an I/O fault from reaching the CPU block while using an alternative I/O block to continue processing, employs common general-purpose processors with a minimum of specialized peripheral circuits. Dual system bus adapters are provided not in the fast-operating CPU portion requiring sophisticated packaging technology, but in the low-speed interface between the CPUs and the I/O bus adapters. This allows the CPUs and I/O bus adapters to be shared by ordinary data processors, workstations, or personal computers while implementing a fault-tolerant computer system. If a one-shot hardware fault occurs in a CPU or in an I/O bus adapter, the faulty component is disconnected from the system so that the system will operate uninterruptedly.

Fault-tolerant computer system

A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which carry out the same operation in synchronism with each other. Each of the processing units includes a copy processor register for designating a processor to read out contents of a memory unit, copying circuits which transfer copies of the stored contents of the memory unit and data to be written into the memory unit in the same order as that of accesses to the memory unit to a memory unit of another processing unit, a copy mode flag indicating that memory copying processing for making the stored contents of the memory unit of the self system and stored contents of the memory unit of the other processing unit coincide with each other is proceeding, and a copy task flag indicating that the processor is reading out, during memory copying processing, the stored contents of the memory unit.

Multiplexed computer system with the capability to copy data from one

The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.

Uninterruptible clock supply apparatus for fault tolerant computer system

A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer channels, the data transfer units share the load of data transfer in the memory copy operation, and when a fault occurs on any data transfer unit during the memory copy operation, the remaining normal data transfer units are used to again transfer data, whereby a memory copy is made at high speed for again synchronizing both the computer systems at the time of recovery from a fault, and system reliability at the time of recovery from a fault is improved.

Dual information processing system having a plurality of data transfer

A method of verifying operation concurrence in maintenance/replacement of twin CPUs employed in a dual-CPU computer wherein a replacement CPU with an initial fault may have been installed by mistake during on-line maintenance/replacement work and a system therefor are disclosed whereby a failure which, without the method and the system, would occur due to the initial fault of the replacement CPU during a dual subsystem synchronous operation carried out thereafter by the computer can be prevented from entailing a system down on both the subsystems.

Method of and system for verifying operation concurrence in

A data communication system carries out transmission and reception of periodic data between a plurality of computers, and especially an improved data communication system which aims at more effective utilization of a system bus in each computer and which also aims at more effective utilization of a data transmission channel transmitting periodic data, so that the load imposed on the system bus during transfer of periodic data in each computer can be minimized, and the rate of occupation of the data transmission channel during transmission and reception of periodic data can also be minimized.

Cyclic data communication system

Method and apparatus for instruction restart processing in a microprogram-controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

System for storing restart address of microprogram, determining the

Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

Suspended instruction restart processing system based on a checkpoint

A processor performs a pipelined parallel processing by an operand effective address calculation unit for calculating an operand effective address necessary to execute an instruction and an instruction execution unit for executing the instruction. A 64 bit width data operation is performed in such a way that a high order 32 bit operation is performed in an arithmetic device in the operand effective address unit and a low order 32 bit operation is performed in another arithmetic device in the instruction execution unit. A carry is transferred from the low order 32 bit arithmetic device to the high order 32 bit arithmetic device. The arithmetic devices thus joined can perform the 64 bit with data operation as an arithmetic device.

Operation control apparatus for a processor having a plurality of

A data processor for execution of tagged data and tagless data has a decoder for discriminating whether the data is tagged or tagless one and in case of a tagged data, separates a tag part and uses the remaining part for address computation. The data processor also comprises a unit for evaluating the tag part and a micro program controller for multi-branching in accordance with the evaluation result of the tag part. The tag evaluating unit includes an extender eliminating part for extracting the tag part from data on a data bus, a plurality of tag part storing registers for storing the tag part from the eliminating part under the control of the micro program controller, and a tag multi-way jump encoder for generating a tag multi-way jump address to feed it to the controller on the basis of the outputs of the registers and a signal from the micro program controller, thereby enabling tag multi-way jump.

Data processor provided with instructions which refer to both tagged and

The present application invention relates to a method for restarting execution of an instruction interrupted due to a page fault. When a page fault occurs during an execution of an instruction, the pertinent page is loaded from an external storage into the main memory and then the access which has caused the page fault is executed again. After N steps of the microprogram that has executed the page fault access, the page fault exception processing is initiated and at the save/restore operation of the content of the microprogram counter, the content of the microprogram is decremented by N, thereby restarting the execution of the instruction beginning from the step of the microprogram which has achieved the page fault access.

Method for restarting execution interrupted due to page fault in a data

An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an output of a mantissa shifter and a signal representing round-up, a carry look-ahead circuit and a circuit for generating a round precision signal are provided. When the overflow takes place, the mantissa is produced as '1'. The operation unit is compatible to single, double and extended precisions recommended by Institute of Electrical and Electronic Engineers (IEEE).

Apparatus for performing floating point arithmetic operations and

A bit slice multiplication circuit operating to slice a multiplier, produce products for the sliced multipliers and a multiplicand and sum the products to obtain the multiplication result. The circuit includes a slicing unit for slicing the multiplicand, multiplying units corresponding in number to the number of sliced multiplicands, and adding units provided in correspondence to the multiplying units and implementing summation for multiplication results from corresponding multiplying units while shifting the sliced portions of the multiplicand at each multiplying operation for sliced multipliers and multiplicands by the multiplying units, the multiplication result being obtained by summing all summation results produced by the adding units.

Bit slice multiplication circuit

Method and apparatus for controlling interruption of a processor. When an external interrupt request having a higher priority level than a current program level is detected in the course of the execution of an instruction, the processing is interrupted and an interexecution interruption is issued. The program level is fixed in this interruption so that the interrupt request is processed as a normal interrupt request at an interruption destination, and the processing is resumed from the interrupted point at a second return instruction after the interrupt processing.

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Mito, Japan

Shinichiro Yamaguchi