Fujitsu Corporation

Aptina Imaging Corporation

Semiconductor Components Industries, LLC

Brillnics, Inc.

Micron Technology Incorporated

The Ritsumeikan Trust

Brillinics Inc.

Shinichiro Matsuo

Isao Takayanagi

Shunsuke Tanaka

Toshinori Otaka

Kazuya Mori

Hidenari Honda

Shusuke Iwata

Katsuhiko Ariyoshi

Junichi Nakamura

Kenji Shibata

Toshiaki Sato

Makoto Watanabe

Shunsuke Okura

Hideki Takauchi

Takeshi Fujino

Masayoshi Shirahata

Mitsuru Shiozaki

Takaya Kubota

Katsuyuki Kawamura

Junichi Katou

Shinji Osawa

Norio Yoshimura

Tsuyoshi Kawamoto

Takeshi Kumaki

A solid-state imaging deviceincludes a pixel portionin which a plurality of pixels including photodiodes are arranged in rows and columns, a reading partfor reading pixel signals from the pixel portion, and a key generation partwhich generates a unique key by using at least one of pixel fluctuation information or reading part fluctuation information. According to this configuration, the tamper resistance of the unique key can be secured and consequently alteration and falsification of images can be prevented.

Solid-state imaging device, method for driving solid-state imaging device, and electronic apparatus with physically unclonable function

This solid-state imaging devicehas: a photosensitive part that includes pixel portions, which are disposed in a matrix, and charge transfer partsfor transferring, by the column, the signal charge of the pixel portions; a plurality of charge storage partsthat accumulate the signal charges transferred by the plurality of charge transfer parts of the photosensitive part; a relay partthat relays the transfer of the signal charges transferred by the plurality of charge transfer parts to each charge storage part; an output partthat outputs the signal charges of the plurality of charge storage parts as electric signals; a first substrateat which the photosensitive unitis formed; and a second substrateat which the charge storage partand output unitare formed. The first substrate and second substrate are stacked together, and the relay partelectrically couples the charge transfer parts of the first substrate to the charge storage parts of the second substrate by means of a connecting parts passing through the substrates outside the photosensitive region of the photosensitive part.

Solid-state imaging device, method for producing solid-state imaging device, and electronic apparatus

A solid state imaging device has: a photosensitive part containing a plurality of charge transfer parts that transfer, in column units, the signal charges of a plurality of photoelectric conversion elements disposed in a matrix; a conversion/output unit that converts, to an electrical signal, the signal charges forwarded by the charge transfer parts; a peripheral circuit part that performs a predetermined process with respect to the electrical signals from the conversion/output part; a relay part that relays the forwarding to the peripheral circuit part of the electrical signal from the conversion/output part; a first substrate where a photosensitive part and the conversion/output part are formed; and a second substrate where the peripheral circuit part is formed. The first and second substrates are stacked together, and the relay part electrically connects the conversion/output part formed at the first substrate to the peripheral circuit part formed at the second substrate.

Solid-state imaging device, method for producing solid-state imaging device, and electronic apparatus using photoelectric conversion elements

An image sensor may include an array of image pixels arranged in rows and columns. Each image pixel arranged along a column may be coupled to a pixel column line. Each pixel column line may be coupled to column memory circuitry via a respective analog-to-digital converter circuit. The column memory circuitry may include multiple column memory circuits, including a spare column memory circuit. If none of the column memory circuits are defective, the spare column memory circuit is idle. If one of the column memory circuits is defective, the spare column memory circuit is engaged to bypass the defective column memory circuit. Configured in this way, the column memory circuitry is provided with column-wise memory repair capabilities.

Image sensors with column memory repair circuitry

An imaging system may include image processing circuitry and an image sensor having a pixel, readout circuitry, and control circuitry. The pixel may have a dual conversion gain gate for switching between a high conversion gain mode and a low conversion gain mode. The pixel may capture a first image signal while the dual conversion gain gate is turned of and a second image signal subsequent to capturing the first image signal while the dual conversion gain gate is turned on. The readout circuitry may identify a selected one of the first and second image signals to output to the image processing circuitry based on the first image signal. In this way, the readout circuitry may output a low conversion gain signal when saturating charge is stored on the charge storage region and may output a high conversion gain signal when insufficient charge is stored on the charge storage region.

Imaging systems and methods for image signal gain adjustment

An image sensor may be provided that includes an image pixel array, analog column circuitry and digital column circuitry. The digital column circuitry may extract a systematic analog signal offset from data received from the analog column circuitry. The digital column circuitry may generate analog signal offset correction values based on the systematic analog signal offsets and provide the analog signal offset correction values to the analog column circuitry. The analog column circuitry may remove signal offsets from subsequently read out image data from the image pixel array using the analog signal offset correction values provided by the digital column circuitry. The image pixel array may include image pixels having color filters of various colors. The digital column circuitry may generate analog signal offset correction values corresponding to each of the various colors.

Imaging systems with digitally controlled analog offset compensation

An imaging system may include an image sensor array and column randomizing multiplexers. The imaging system may include a data output circuit and image readout circuitry such as analog amplifiers, analog-to-digital converters, and memory circuits. The column randomizing multiplexers may include a first column randomizing multiplexer between the image sensor array and at least some of the image readout circuitry. The first column randomizing multiplexer may randomly connect columns of the image sensor array to the image readout circuitry. The connections made by the first column randomizing multiplexer may be randomized as each row of the image sensor array is read out. The column randomizing multiplexers may include a second column randomizing multiplexer between at least some of the image readout circuitry and the data output circuit. The second column randomizing multiplexer may reorder image data for the image readout circuitry.

Imaging systems with column randomizing circuits

A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to implement the buffers based on design constraints. In an exemplary embodiment, the line buffers may be arranged in any buffer topology arrangement meeting the average number of branches and the number of stages design constraints.

Buffering technique using structured delay skewing

A latch-type level converter has a signal-input transistor, a latch, and a clock-input transistor. The signal-input transistor, which is a high-voltage transistor, receives an input signal, and the latch holds data of the input signal received by the signal-input transistor. The clock-input transistor controls the operation in accordance with a clock. According to the latch-type level converter, not only can low-amplitude signals be accurately amplified, but also input signals having a common-mode voltage higher than the supply voltage can be received.

Latch-type level converter and receiver circuit accurately amplifying low-amplitude signals and receiving common-mode input signals higher than a supply voltage

There is disclosed the relay apparatus which can detect the data length and the communication time interval of the received packet, and based on these results of detection, set the communication band of a channel for sending out this received packet.

Relay apparatus

An AWN (&num; ) extracts a destination PBX node number from destination address information included in an N-ISDN SETUP message received from a PBX, decides the type of an audio CODEC corresponding to the PBX node number, and selects an audio CODEC corresponding to the type. An AWN (&num; ) extracts destination PBX node number from destination address information included in an N-ISDN SETUP message received from an AWN (&num; ), decides the type of an audio CODEC corresponding to the PBX node number, and selects an audio CODEC corresponding to the type. Thus, an audio CODEC is selected corresponding to a destination route. Consequently, a digital one-link connection is accomplished.

ATM-WAN audio communication selecting system

A method of controlling detouring in an integrated network which includes communication devices includes the steps of registering routes at a communication device connected to terminal devices of respective media types such that the routes include a main route and a detour route with respect to each of the media types, and establishing a connection along the detour route registered for a media type upon finding unavailability of the main route registered for the media type when a call of the media type is requested from one of the terminal devices.

Method of controlling detouring in integrated network and communication device based on such method

Only one ATM call setting path is set between two ATM-WAN nodes, and ATM communication paths for audio signals of a number corresponding to the number of calls are set. If call setting N-ISDN signals are transmitted from a PBX-A, the IWF of the ATM-WAN nodes on a calling party side stores the call setting N-ISDN signals in ATM cells transparently as they are, and sends the ATM cells to a common ATM call setting path. If call setting channel associated signals are transmitted from a PBX-B, the IWF of the ATM-WAN nodes on a calling party side converts the call setting channel associated signals to call setting N-ISDN signals, stores the converted signals in ATM cells, and sends the ATM cells to a common ATM call setting path.

Apparatus for transmitting cells, with audio interwork function

A network system of the present invention has a TDM network including TDM switches and an ATM network including communication devices connected the TDM switches. Each of the communication devices comprises a first call setting unit setting, when receiving a call setting request from the transmitting side TDM switch, a call between this communication device and the receiving side communication device, a specifying unit specifying, if the first call setting unit is unable to set the call, any one of TDM switches as a detour TDM switch, a storing unit stored with detour information for setting the call between the detour TDM switch and the receiving side TDM switch, a reading unit reading the detour information when the specifying unit specifies the detour TDM switch, a second call setting unit setting a call between the communication device and a detour communication device, and a unit making, when the second call setting unit sets the call, the detour communication device transmit a call setting request containing the detour information read by the reading unit to the detour TDM switch.

Growing community of inventors

Kawasaki, Japan

Shinichiro Matsuo