Hitachi, Ltd.

ShinIchiro Kimura

Toru Kaga

Tokuo Kure

Hideo Sunami

Eiji Takeda

Masahiro Moniwa

Yoshifumi Kawamoto

Yoshio Sakai

Naotaka Hashimoto

Atsushi Hiraiwa

Makoto Ohkura

Terunori Warabisako

Dai Hisamoto

Haruhiko Tanaka

Masanobu Miyao

Kikuo Kusukawa

Takashi Kobayashi

Toshiyuki Mine

Shinpei Iijima

Jiro Yugami

Kiyoshi Miyake

A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

Semiconductor memory device

Semiconductor memory device having stacked capacitors

A semiconductor device such as FET or charge coupled device, having a channel or a charge coupled portion provided in a thin semiconductor layer which is nearly perpendicular to the substrate and to which the necessary electrode such as the gate electrode and the necessary insulating layer are added can maintain the necessary amount of electric current by securing the height of the semiconductor layer and also can have its plane size reduced minutely. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.

Method of manufacturing a semiconductor device having silicon islands

Method of fabricating stacked capacitor cell memory devices

An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.

Method for manufacturing a semiconductor device and a semiconductor

A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.

Semiconductor memory device having stacked capacitor cells

A semiconductor device, such as an FET or a charge coupled device, is provided having a channel or a charge coupled portion formed in a thin semiconductor layer which is substantially perpendicular to the substrate. Necessary electrodes, such as the gate electrode, and necessary insulating layers can be added at the thin semiconductor layer, and can maintain the necessary amount of electric current by securing the height of the semiconductor layer. The structure has the advantage that it can have its plane size reduced. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.

Semiconductor device and semiconductor memory device

Disclosed is a semiconductor device including a charge storage capacitor having a storage electrode which is electrically connected to a switching transistor through a contact hole provided in an insulator and which has a greater film thickness than the radius of the contact hole, at least a part of the storage electrode being disposed above a data line. It is possible to reduce the memory cell area while preventing lowering in the capacitance, and thus realize high density and high integration of semiconductor devices.

Semiconductor device having an arrangement of IGFETs and capacitors

A megabit dynamic random access memory realizing high integration and high reliability is disclosed. The need for an allowance for photomask alignment which is carried out to produce a stacked capacitor memory cell is eliminated. The plate electrode of each memory cell is isolated from the corresponding data line in a memory array by means of an insulating film which is self-alignedly provided around the plate electrode.

Semiconductor memory having stacked capacitor

The side wall part of a recess dug in a Si substrate is used as the major part of the electrode surface of a capacitor, whereby the electrode area is enlarged without enlarging a plane area. Thus, a desired capacitor capacitance can be attained without increasing the breakdown of an insulator film ascribable to the conventional approach of thinning of the insulator film. In addition, a vertical switching transistor is formed on the Si substrate, whereby the Si substrate can be entirely utilized for the formation of the capacitor.

Semiconductor memory and method of producing the same

The present invention relates to a highly packaged semiconductor memory, and more particularly to a memory cell having a trench capacitor for use in a CMOS memory. The present invention discloses a semiconductor memory employing memory cells each constructed of a trench type charge storage capacitor formed within a substrate, and a switching transistor; one electrode of the capacitor having a sheath-shaped structure which is electrically continuous with the Si substrate at a bottom of a groove and whose sideward periphery is covered with an insulator, the other electrode of the capacitor having a part which is buried inside the sheath electrode and another part which is electrically connected with an impurity diffused layer to function as a source region of the transistor. Further, a structure in which a voltage of 1/2 V.sub.cc can be applied to a plate electrode of a memory cell having a trench capacitor is disclosed.

Semiconductor memory having trench capacitor formed with sheath electrode

This invention relates to a very large scale dynamic random access memory, and discloses a memory cell having a reduced step on the device surface portion and being hardly affected by incident radioactive rays. In a semiconductor memory consisting of a deep hole bored in a semiconductor substrate, a capacitor formed on the sidewall portion at the lower half of the deep hole and a switching transistor formed immediately above the capacitor, at least the half of a word line constituting the gate of the switching transistor is buried in an elongated recess formed at the surface portion of the semiconductor substrate.

Dynamic random access memory having buried word lines

A process for producing a memory cell having a stacked capacitor. As the reduction in device size of memory cells progresses, it becomes difficult to obtain a satisfactorily large capacitance even with a stacked capacitor structure. To enable a larger capacitance to be obtained for the same occupied area, projections and recesses are provided on the surface of a capacitor electrode. It is possible, according to the process, to readily produce projections and recesses for increasing the storage capacitance.

Growing community of inventors

Hachioji, Japan

ShinIchiro Kimura