Hitachi, Ltd.

Renesas Electronics Corporation

Renesas Technology Corp.

Other

Nec Corporation

Nec Electronics Corporation

Elpida Memory, Inc.

Renesas Electronics Corportion

Shinichiro Kimura

Digh Hisamoto

Kan Yasui

Toshiaki Yamanaka

Hideyuki Matsuoka

Tetsuya Ishimaru

Tomonori Sekiguchi

Takeshi Sakata

Nozomu Matsuzaki

Tokuo Kure

Daisuke Okada

Akio Nishida

Ryuta Tsuchiya

Eiji Takeda

Kiyoo Itoh

Hiromasa Noda

Natsuki Yokoyama

Nobuyuki Sugii

Yoshifumi Kawamoto

Takashi Ishigaki

Yusuke Morita

Riichiro Takemura

Satoru Yamada

Norio Suzuki

Norikatsu Takaura

Osamu Tsuchiya

Eiichi Murakami

Toru Kaga

Ryo Nagai

Kikuo Kusukawa

Atsushi Ogishima

Masakazu Aoki

Shoji Shukuri

Hitoshi Tanaka

Yoshio Sakai

Kousuke Okuyama

Naotaka Hashimoto

Yasuhiro Shimamoto

Masahiko Hiratani

Tomoyuki Hamada

Jiro Yugami

Masatada Horiuchi

Hiroyuki Yoshimoto

Ken Yamaguchi

Kazuhiko Sagara

Kazunori Umeda

Tatsuya Teshima

Kazuhiko Kajigaya

Toshiaki Iwamatsu

Shuji Ikeda

Kenichi Takeda

Katsutaka Kimura

Yoshinobu Nakagome

Satoru Hanzawa

Iwao Takemoto

Kenichi Kuroda

Masataka Minami

Tsugio Takahashi

Shinichi Saito

Hiroshi Miki

Makoto Ohkura

Kiyonori Oyu

Nobuyoshi Kobayashi

Yasushi Goto

Hideo Sunami

Shinichi Minami

Yasuko Yoshida

Masanobu Miyao

Kazunori Tsujimoto

Masayuki Nakamura

Kazuyoshi Torii

Ryo Haruta

Shiro Kamohara

Kiichiro Mukai

Takashi Nishida

Terunori Warabisako

Hisao Asakura

Junji Shigeta

Dai Hisamoto

Takashi Tokuyama

Yasushiro Nishioka

Renichi Yamada

Toshiyuki Yoshimura

Shimpei Iijima

Tomoko Sekiguchi

Tsuyoshi Kachi

Kikuo Watanabe

Toru Koga

Shuji Shukuri

A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

Fabrication method and structure of semiconductor non-volatile memory device

Semiconductor non-volatile memory device

In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.

Semiconductor device, method for manufacturing same, and semiconductor storage device

An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

Semiconductor nonvolatile memory device

A device and a method for manufacturing the same in which with device includes a single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) in which well diffusion layer regions, drain regions, gate insulating films, and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in the same steps. The bulk-type MISFET and the SOI-type MISFET are formed on the same substrate, so that board area is reduced and a simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

Method for manufacturing a semiconductor device by forming portions thereof at the same time

There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. The first elevated layer is thicker than the second elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

Method of manufacturing a semiconductor device having elevated layers of differing thickness

A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.

Semiconductor device

Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.

SiGe MOSFET semiconductor device with sloped source/drain regions

In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

Nonvolatile semiconductor memory device

A light emitting diode demonstrating high luminescence efficiency and comprising a Group IV semiconductor such as silicon or germanium equivalent thereto as a basic component formed on a silicon substrate by a prior art silicon process, and a fabricating method of waveguide thereof are provided. The light emitting diode of the invention comprises a first electrode for implanting electrons, a second electrode for implanting holes, and a light emitting section electrically connected to the first and the second electrode, wherein the light emitting section is made out of single crystalline silicon and has a first surface and a second surface facing the first surface, wherein with respect to plane orientation (100) of the first and second surfaces, the light emitting section crossing at right angles to the first and second surfaces is made thinner, and wherein a material having a high refractive index is arranged around the thin film section.

Semiconductor LED, opto-electronic integrated circuits (OEIC), and method of fabricating OEIC

Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.

Semiconductor device and manufacturing method of the same

Split-gate type memory device

Growing community of inventors

Kunitachi, Japan

Shinichiro Kimura