Fuji Xerox Co., Ltd.

Shinichi Yasunaga

Tohru Mihara

Mitsumasa Narahara

Yuji Yatsuda

Fujio Moriguchi

Akira Mihara

Yoshinao Kondoh

Nobuhisa Kato

Yasunao Misawa

Kunihito Sato

Yasuo Wakamori

Kazumi Yamauchi

An ink-jet recorder is disclosed which has an arrangement of a plurality of heat-generating elements, drivers for driving the heat-generating elements, and a drive circuit for controlling the drivers according to image data, wherein the drive circuit includes; a split-block drive circuit that divides the plurality of heat-generating elements into a plurality of blocks, and drives the heat-generating elements on a block-by-block basis in a time-sharing manner, and a data retaining circuit for retaining print data; and the split-block drive circuit that; drives each of the blocks of the heat-generating elements at printing operations, using a pre-pulse during which ink is not squirted and a main pulse during which ink is squirted; and drives another group of heat-generating elements differing from the currently-driven group of heat-generating elements, during intervals between the pre-pulse and the main pulse.

Ink-jet recorder having a driving circuit for driving heat-generating

A fuzzy logic circuit for operating a fuzzy logic with 'fuzziness' taken into account has an operation section memory unit in which the result of operation to be outputted in response to an input is stored in an address specified by the input, the result of operation being rewritable, whereby the change in the contents of a fuzzy logic operation to be performed can be handled merely by rewriting the contents of the operation section memory unit.

Programmable fuzzy logic circuits

A coincidence circuit for detecting when n-bit binary input data coincides with the current value of an n-bit counter. A plurality of '1' detecting circuits determine, when a corresponding input bit is one, whether a corresponding counter bit is also one. A first-coincidence detecting circuit determines the first time that all the '1' input bits have corresponding '1' clock bits. Each '1' detecting circuit includes an inverter and a NOR gate. The first-coincidence detecting circuit includes an OR gate and a latch circuit.

Coincidence circuit

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Kanagawa, Japan

Shinichi Yasunaga