Kabushiki Kaisha Toshiba

Abb K.k.

Thomson Licensing

Shinichi Yasuda

Masato Oda

Mari Matsumoto

Kosuke Tatsumura

Koichiro Zaitsu

Shinobu Fujita

Tetsufumi Tanamoto

Keiko Abe

Takao Marukame

Kazutaka Ikegami

Yinghao Ho

Kumiko Nomura

Atsuhiro Kinoshita

Atsushi Shimbo

Kiwamu Sakuma

Yuichiro Mitani

Yoshifumi Nishi

Satoshi Takaya

Haruka Kusai

Yoshihisa Iwata

Tatsuya Kishi

Yoshihiro Ueda

Koichi Abe

Hiroki Noguchi

Atsushi Kawasumi

Reika Ichihara

Shinji Miyano

Koichi Fujisaki

Mizuki Ono

Takahiro Kurita

Ryuji Ohba

Daisuke Hagishima

Masafumi Mori

Shuou Nomura

Shogo Tsubouchi

Noriko Inoue

Haiyang Peng

Akira Tomita

Ryusuke Murakami

Satoru Morishige

Yukinori Miyamoto

An integrated circuit of an embodiment includes: a logic circuit; and a switch circuit, the logic circuit including: a first memory; a look-up table circuit having a first output terminal; a first selection circuit having a first input terminal connecting to the first output terminal, a second input terminal receiving scan input data, and a second output terminal, the first selection circuit selecting one of the first and second input terminals and connect the selected one to the second output terminal; a flip-flop having a third input terminal connected to the second and third output terminals; and a second selection circuit having a fourth and fifth input terminals connected to the third output terminal and the first output terminal respectively, and a fourth output terminal, the second selection circuit selecting one of the fourth and fifth input terminals and connect the selected one to the fourth output terminal.

Integrated circuit, test method for testing integrated circuit, and electronic device

A semiconductor integrated circuit of an embodiment includes: first to fifth wiring lines; a first OTP memory element including a first and second terminals connected to the first and second wiring lines; a first p-channel transistor including a source and drain terminals connected to the first and third wiring line, and a gate terminal receiving a first control signal; a first n-channel transistor including a source and drain terminals connected to the first and fourth wiring lines, and a gate terminal receiving a second control signal; a second p-channel transistor including a source and drain terminals connected to the second and third wiring lines, and a gate terminal receiving a third control signal; and a second n-channel transistor including a source and drain terminals connected to the second and fifth wiring lines, and a gate terminal receiving a fourth control signal.

Semiconductor integrated circuit

A memory circuit according to an embodiment includes: a first inverter circuit including a first p-channel MOS transistor and a first n-channel MOS transistor; a second inverter circuit cross-coupled with the first inverter and including a second p-channel MOS transistor and a second n-channel MOS transistor; a third n-channel MOS transistor in which one of a source and drain terminals is connected to a first output terminal of the first inverter circuit, and a gate terminal is connected to a first wiring line; a fourth n-channel MOS transistor connected to the third n-channel MOS transistor; a fifth n-channel MOS transistor in which one of a source and drain terminals is connected to a second output terminal of the second inverter circuit; and a sixth n-channel MOS transistor connected to the fifth n-channel MOS transistor.

Memory circuit and electronic device

According to one embodiment, a random number generator includes a first circuit which outputs a second oscillation signal having a predetermined duty ratio on the basis of a first oscillation signal, a second circuit which latches values on the basis of the second oscillation signal and a clock having a frequency lower than a frequency of the second oscillation signal, a third circuit which outputs a control signal on the basis of the values, and a fourth circuit which controls the first circuit on the basis of the control signal.

Random number generator

A semiconductor integrated circuit according to an embodiment includes: first to third wiring lines; first memory elements disposed in a cross region between the first wiring lines and the second wiring lines; second memory elements disposed in a cross region between the first wiring lines and the third wiring lines; a first write control circuit connected to the first wiring lines: a first circuit connected to one of the second wiring lines and supplying a first potential; a second circuit connected to the other one of the second wiring lines and supplying a second potential lower than the first potential; SRAM cells connected to the third wiring lines; and a selection circuit including input terminals electrically connected to the first wiring lines and an output terminal, the selection circuit connecting one of the input terminals to the output terminal in accordance with an input signal.

Reconfigurable semiconductor integrated circuit

A semiconductor integrated circuit according to an embodiment includes: first to third wirings; first current limiters corresponding to the first wirings; second current limiters corresponding to the second wirings; third current limiters corresponding to the third wirings; first drivers corresponding to the first current limiters; second drivers corresponding to the second current limiters; third drivers corresponding to the third current limiters; and a first array and a second array, wherein the first array comprising: fourth wirings corresponding to the first wirings; fifth wirings corresponding to the second wirings; first transistors corresponding to the first wirings; second transistors corresponding to the second wirings; and first resistive change elements arranged in intersecting areas of the fourth wirings and the fifth wirings, respectively, the first resistive change elements including a first terminal connected to corresponding one of the fourth wirings and a second terminal connected to corresponding one of the fifth wirings.

Semiconductor integrated circuit having programmable logic device and resistive change elements

A configuration memory circuit according to an embodiment includes: a first and second wirings; and a first to eighth transistors, the first and fourth transistors having a first-conductive-type, the second, third, fifth, and sixth transistors having a second-conductive-type, the first to third transistors being connected in series, the fourth to sixth transistors being connected in series, gates of the first and third transistors being connected to the first wiring, one of a source and a drain of the seventh transistor, and the first wiring, a gate of the second transistor being connected to a third wiring, gates of the fourth and sixth transistors being connected to the second wiring, one of a source and a drain of the eighth transistor, and the second wiring, a gate of the fifth transistor being connected to the third wiring, gates of the seventh and eighth transistors being connected to a fifth wiring.

Configuration memory circuit

An authentication server according to embodiments performs statistical processing on a plurality of pieces of ID data acquired from an electronic device including a PUF circuit generating the pieces of ID data (Sto S), determines whether the plurality of pieces of ID data are physical random numbers based on a result of the statistical processing (S), and when the plurality of pieces of ID data are determined to be physical random numbers, recognizes the result of authentication of the electronic device as a success of authentication (S), and when the plurality of pieces of ID data are determined not to be physical random numbers, recognizes a result of authentication of the electronic device as a failure of authentication (S).

Authentication server, authentication system, and authentication method

According to an embodiment, an arithmetic device is configured to receive M input signals each representing a two-state value and M coefficients to output an output signal representing a two-state value. The device includes a positive-side current source, a negative-side current source, M cross switches, a coefficient memory unit, and a comparator. The positive-side current source is configured to output a first voltage corresponding to a value of 1/L of the current output from a positive-side terminal. The negative-side current source is configured to output a second voltage corresponding to a value of 1/L of the current output from a negative-side terminal. The memory unit includes M cells corresponding to the respective M coefficients. The comparator is configured to output an output signal having a value corresponding to a comparison result of the first voltage with the second voltage. Each M cell includes a first resistor and a second resistor.

Arithmetic device

An integrated circuit according to an embodiment includes: first and second wiring lines; a memory device including a first and second terminals connected to the first and second wiring line respectively; a first transistor including a high-k metal gate; a first circuit applying a first write voltage between the first and the second terminals, and switch the resistance of the memory device from a high-resistance state to a low-resistance state; a second circuit reading the resistance of the memory device, and comparing a read value of the resistance with a predetermined value; a third circuit lowering a threshold voltage of the first transistor when the read value of the resistance is greater than the predetermined value; a fourth circuit applying a second write voltage between the first and second terminals after the threshold voltage is lowered; and a fifth circuit raising the threshold voltage of the first transistor.

Integrated circuit including memory, and write method

An integrated circuit according to an embodiment includes: resistive change elements disposed in intersection regions between first and second wiring lines; a first driver driving the first wiring lines; a second driver driving the second wiring lines; a control circuit controlling the first and second drivers; first current limiter circuits corresponding to the first wiring lines, each of the first current circuits each limiting a maximum current flowing in corresponding one of the first wiring lines to a value not greater than one of a first to third current values; and second current limiter circuits corresponding to the second wiring lines, the second current limiter circuits each limiting a maximum current flowing in corresponding one of the second wiring lines to a value not greater than one of the first to third current value, the limiting current of the selected element being higher than that of the unselected element.

Semiconductor integrated circuit with resistive change elements intersect with first and second plurality wiring lines, control circuit and plurality of current limiter circuits corresponding to the first and second wiring lines

A semiconductor device of an embodiment includes: a logical block including at least one first input terminal; at least two first output terminal; a first wiring line group; a second and third wiring line groups including a plurality of shorter wiring lines than wiring lines of the first wiring line group; a fourth and fifth wiring line groups; a first to fourth switch circuits; a first logical element including second and third input terminals connected to at least one of wiring lines of the fourth wiring line group, and a second output terminal connected to one of the at least two first output terminals; and a second logical element including fourth and fifth input terminals connected to at least one of the wiring lines of the fifth wiring line group, and a third output terminal connected to another of the at least two first output terminals.

Semiconductor device including logical blocks, wiring groups, and switch circuits

An integrated circuit of an embodiment includes: a first to third wiring lines; a first and second input terminals connected to the second and third wiring lines respectively; a first and second control terminals; a first switch element disposed between the first and second wiring lines, the first switch element including a first and second terminals connected to the first and second wiring lines respectively; a second switch element disposed between the first and third wiring lines, the second switch element including a third and fourth terminals connected to the first and fourth terminals connected to the first and third wiring lines respectively; a first transistor including a source and a drain, one of the source and the drain being connected to the first wiring line; a select circuit including a fifth to eighth terminals; and a logic circuit including a ninth to eleventh terminals.

Integrated circuit and electronic apparatus

According to an embodiment, an authentication system includes a physical device, a calculator, and an authenticator. The physical device includes a data source which outputs a data sequence along time series. The calculator performs, using hidden Markov model, probability calculation on an ID which is based on the data sequence obtained from the physical device. The authenticator authenticates the physical device based on calculation result of the calculator.

Authentication system, authentication device, and authentication method

A memory element according to an embodiment includes: first through fourth impurity layers arranged in a semiconductor layer including first to third portions; a first gate wiring line disposed on the first portion located between the first and second impurity layers; a second gate wiring line disposed on the second portion located between the second and third impurity layers; a third gate wiring line disposed on the third portion located between the third and fourth impurity layers; a first insulating layer disposed between the first portion and the first gate wiring line; a second insulating layer disposed between the second portion and the second gate wiring line; a third insulating layer disposed between the third portion and the third gate wiring line; first wiring line electrically connected to the first through third gate wiring lines; and second wiring line electrically connected to the first through fourth impurity layers.

Growing community of inventors

Tokyo, Japan

Shinichi Yasuda