Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Sanyo Semiconductor Co., Ltd.

Shinichi Yamasaki

Masanori Okubayashi

Susumu Yamada

Hisao Ishii

Toru Watanabe

Kazuyoshi Oshima

A video signal processing integrated circuit comprising: a test signal generation circuit configured to generate a test signal in conformity with video additional data superimposed on a video signal; a data slicer configured to binarize the test signal through comparison with a slice level, the test signal being supplied from the test signal generation circuit; and a data processing circuit configured to perform data processing of the video additional data binarized by the data slicer.

Video signal processing integrated circuit

A data slicer circuit is disclosed which comprises a control circuit to output a digital signal that increases or decreases by a constant value difference depending on the level of an input signal when the input signal is sampled at a given frequency; a conversion circuit to convert the digital signal to an analog signal; and a comparison circuit to compare the video signal with the analog signal, the comparison circuit outputting the result of the comparison as the input signal to the control circuit, wherein the analog signal corresponding to the result of the comparison of the comparison circuit is used as a slice level for separating the data from the video signal.

Data slicer circuit

A comparator system for comparing a level of an input signal with a level of a reference signal comprises a first comparator configured to input the input signal to one of input terminals thereof and the reference signal to the other of input terminals thereof, a second comparator configured to input the reference signal to one of input terminals thereof and the input signal to the other of input terminals thereof, and a control circuit configured to input an output of the first comparator and an output of the second comparator. The control circuit selects one of the outputs of the first and second comparators quicker in level change timing, and controls an output signal of the control circuit at the level change timing of the selected output.

Comparator system and method for comparing an input signal with a reference level using said system

When data are to be written in an EEPROM (1), a CPU (2) sets a flag (12). A voltage booster (13) boosts the power voltage in compliance with the setting of the flag (12). A voltage boost detector (14) detects whether the output of the voltage booster (13) is in voltage boost state. If the output of the voltage booster (13) is not in voltage boost state, a latch (15) is reset and the EEPROM (1) is not permitted to switch to write mode. As a result, it is possible to prevent incorrect data writing in the EEPROM (1) even when the flag (12) has been incorrectly set.

Microcomputer capable of preventing writing errors in a non-volatile

In a signal-strength-peak detecting circuit, tuning frequencies by a tuning circuit are periodically varied. Wide band seek is performed according to a signal level of the varied frequencies. When the signal level is greater than a predetermined value, a fine tuning circuit varies tuning frequencies to perform narrow band seek. Further, change of signal levels is detected during narrow band seek to decide whether the peak of the signal level is trapezoidal or rounded. When the peak is decided to be rounded, the maximum value is used as the peak. On the other hand, when the peak is decided to be trapezoidal, the central point of an upper side of the trapezoid is selected as an optimum peak.

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Hanyu, Japan

Shinichi Yamasaki