Renesas Electronics Corporation

Shinichi Watarai

Takayuki Sasaki

Atsushi Hiraiwa

Motoshige Igarashi

Naozumi Morino

Masao Sugiyama

Hiroshi Yanagita

Toshiaki Ito

Kazutoshi Oku

There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Semiconductor device having a plurality of shallow wells

Semiconductor device

Growing community of inventors

Tokyo, Japan

Shinichi Watarai