Fujitsu Corporation

Sony Semiconductor Solutions Corporation

Shinichi Tsuchida

Takahiro Okada

Jun Ueshima

Tadaaki Yuba

A calculation processing apparatus is disclosed. In one example, an exclusive memory stores an exclusive area different from an address space of a processor. A data transfer unit performs transfer processing of data items between the address space and the exclusive memory. A calculation processing unit performs calculation processing between the data items stored in the exclusive memory. A command resistor group holds each command of command columns received from the processor in each resistor. A state machine manages a state of processing in the data transfer unit and the calculation processing unit. A control unit controls the command resistor group so as to hold the command and controlling the command resistor group such that the commands held by the command resistor group are fed to any of the data transfer unit and the calculation processing unit depending on the state.

Calculation processing apparatus and information processing system

A debug work is performed with respect to states after execution of a plurality of commands which is collectively issued from a processor to an arithmetic processing apparatus. A command register group holds commands issued from the processor in respective registers with a command chain including a plurality of commands as a unit. A command processing section processes the commands supplied from the command register group. A state machine manages processing states of the commands in the command processing section. A control section previously sets a condition under which stop is to be performed in the command chain as a stop condition and causes to stop the processing in the command processing section on the basis of the previously set stop condition and the processing states managed in the state machine.

Arithmetic processing apparatus and information processing system

A multiplexing apparatus multiplexes two or more data streams and output to an arbitrarily selected circuit, and includes a time division switch for multiplexing inputted data and outputting the multiplexed data to a selected circuit, and a memory unit which stores real control data for controlling actual connection operations of the time division switch and virtual control data for controlling virtual connection operations.

Multiplexing method, a multiplexing apparatus and a network therewith

An encryption unit uses part of a pseudo random number generated by a random number generator to encrypt data to be transferred which are stored in the payload of a cell. A counter information assigning section inserts counter information indicating the order in which the cell was sent into that payload. A random number generator on a receiving side generates the same pseudo random number as the random number generator on a sending side. A counter information analysis section identifies the position of the part of the pseudo random number to be used in the encryption unit based on the counter information extracted from the received cell, and has the random number generator on the receiving side output that part of the pseudo random number. The encrypted transferred data are extracted from the received cell, and these transferred data are decrypted using the part of the pseudo random number output from the random number generator on the receiving side.

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Kanagawa, Japan

Shinichi Tsuchida