Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Shinichi Tashiro

Toshiya Fujii

Takeshi Fujita

Akiyoshi Kohno

Yoshiaki Sone

Ryoichi Nagayoshi

Isao Ihara

Kazuyuki Inokuma

Kunihiro Imamura

Tsuyoshi Hasuka

Katsumi Takeda

Keijiro Itakura

The solid-state image pickup device of the invention includes: a plurality of optoelectronic transducers arranged in an array; a plurality of vertical transfer sections each for reading charges from optoelectronic transducers and vertically transferring the read charges; a horizontal transfer section; a charge detection section for converting the horizontally transferred charges to signal voltages and the like; and a control section. The control section outputs signals so as to obtain either a signal corresponding to the sum of charges from an optoelectronic transducer belonging to one column and belonging to one of alternately selected rows and an optoelectronic transducer belonging to a column adjacent to the one column and belonging to a row other than the alternately selected rows, or a signal corresponding to the sum of charges from optoelectronic transducers belonging to a same column, every predetermined even number of continuous rows of optoelectronic transducers.

Solid-state image pickup device, drive method therefor and camera

The present invention provides a solid-state image sensing device that can reduce at least the number of pixels arranged in the horizontal direction and can output high quality picture signals at high speed without generating moire or alias. The solid-state image sensing device includes vertical transfer partsin which signal charges read out from photoelectric conversion partsarranged bidimensionally are transferred in the vertical direction stage by stage, a horizontal transfer partin which signal charges received from the vertical transfer partsare transferred in the horizontal direction, and a control unit that controls transfer operations of the vertical transfer partsand horizontal transfer part, wherein vertical last stages of the vertical transfer partshave transfer electrodes formed to have identical configurations repeated every 2n+1 (n denotes an integer of 1 or higher) columns, and vertical last stages of columns other than one column among the 2n+1 columns or all vertical stages are provided with transfer electrodes that are independent of those of the other vertical last stages.

Solid-state image sensing device and camera using the same

The present invention provides a solid-state image sensor, a solid-state image sensing apparatus, and a camera realizing a high-speed operation, all operable to output signal charges so as to maintain the light sensitivity and generate high-quality video signals free from moir&#xe9; and aliased signals even if the number of pixels making up one frame of an image is reduced. The solid-state image sensor comprises a plurality of photoelectric converters, vertical transfer groups, and a horizontal transfer unit disposed at one side of the vertical transfer groups. Each vertical transfer group includes 2n+1 vertical transfer units, where n is an integer of 1 or more. Each vertical transfer unit includes a plurality of transfer electrodes arranged in columns and charge storage units receiving and storing charges from the photoelectric converters. In n out of the 2n+1 vertical transfer units, predetermined transfer electrodes disposed near the horizontal transfer unit are independent transfer electrodes.

Solid-state image sensor, solid-state image sensing apparatus, camera, and method for controlling a solid-state image sensor

To reduce the amount of data that should be stored on a memory-built-in timing generator for generating timing pulses for use to drive a solid-state imaging device, V- and H-counters, three ROMs, V- and H-comparators and combinatorial logic circuit are provided. The V- and H-counters perform a count operation responsive to vertical and horizontal sync signal pulses as respective triggers. One of the ROMs stores time-series data representing a logical level repetitive pattern of an output pulse train. The other two ROMs store edge data representing at what counts of the V- and H-counters control pulses should change their logical levels. The V- and H-comparators and the combinatorial logic circuit change the logical levels of the control pulses when the counts of the V- and H-counters match the edge data. The comparators and logic circuit also output, as the timing pulses, results of logical operations performed on the output pulse train, represented by the time-series data, and the control pulses.

Timing generator for solid-state imaging device

An image sensing apparatus is provided, in which the charges of four pixels that are adjacent in the horizontal direction and the vertical direction are mixed and output, and combinations of pixel mixings in the horizontal direction are changed at each line, so that signals after four pixels have been mixed are in an offset sampling relation for each line. Furthermore, a color filter of, for example, an RGB primary color stripe arrangement is provided such that three independent color signals can be attained in both a still picture image sensing (all pixel readout) mode and in a moving picture image sensing (four pixel mixing readout) mode.

Image sensing apparatus

A counter circuit includes counting stages of n bits where n is a natural number. The counter circuit also includes a logic decoding circuit for determining the inputs of the counting stages, a logic circuit for adjusting the number of simultaneous changes so that the number of simultaneous changes of the logic decoding circuit can be made uniform, and a logic circuit for adjusting the load capacitance of the counting stages so that the load capacitance can be made uniform. The counter circuit may also include a test logic circuit for creating a test wave form on the basis of the outputs from the logic circuits for adjusting the number of simultaneous changes and the logic circuits for adjusting the load capacitance. Accordingly, it is possible to detect a failure of the logic circuits for adjusting the number of simultaneous changes and the logic circuits for adjusting the load capacitance which does not effect the counting output.

Driving circuit for solid-state image sensor and counter circuit used

A counter circuit which incurs a uniform number of logic changes whether the clock signal is rising or falling is used in both a first counter circuit for measuring the reference signal for horizontal scanning period and a second counter circuit for measuring signals in the vertical blanking period. Since the number of logic changes of the flip-flops with respect to the clock signal is uniform, a driving circuit for a solid-state image sensor is realized in which noise in the vertical blanking period does not appear in the video period even if by using 1H delay line.

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Osaka, Japan

Shinichi Tashiro