Kabushiki Kaisha Toshiba

Mitsubishi Denki Kabushiki Kaisha

The University of Tokyo

Sumitomo Chemical Company, Limited

National Institute of Advanced Industrial Science and Technology

Mitsubishi Electric Corporation

Yamaha Corporation

Japan Science and Technology Agency

Shinichi Takagi

Naoharu Sugiyama

Tsutomu Tezuka

Tomohisa Mizuno

Hiroshi Aruga

Kiyohide Sakai

Mitsuru Takenaka

Masahiko Hata

Koji Usuda

Yoshihito Hirano

Masao Imaki

Yasunori Nishimura

Toshifumi Irisawa

Akihiro Adachi

Makoto Sato

Tsutomu Sato

Ichiro Mizushima

Yoshitaka Tsunashima

Mie Matsuo

Masafumi Yokoyama

Hisashi Yamada

Atsushi Kurobe

Kenji Masuda

Tetsuji Yasuda

Noboru Fukuhara

Toshinori Numata

Yuji Urabe

Junji Fujino

Tomoyuki Takada

Hiroaki Matsui

Junji Koga

Hideki Takagi

Katsunori Suzuki

Hitoshi Tabata

Kenji Natori

Makoto Satou

Akinobu Suzuki

Taro Itatani

Isao Oshima

Takenori Osada

Shinichi Kaneko

Osamu Ichikawa

Tetsutsugu Hamano

Noriyuki Miyata

Hiroyuki Ishii

Ken Matsuoka

Takeshi Aoki

Jaehoon Han

SangHyeon Kim

Toshiharu Kato

Shu Nakaharai

Yoshihiro Hashimoto

Yasunori Nisimura

Kimihiko Kato

Jae-Hoon Han

A tunneling field effect transistor according to an embodiment of the present invention includes: a first semiconductor layer having a first conductive type; a second semiconductor layer having a second conductive type and realizing a heterojunction with respect to the first semiconductor layer in a first region; a gate insulating layer over the second semiconductor layer in the first region; a gate electrode layer over the gate insulating layer; a first electrode layer electrically connected to the first semiconductor layer; a second electrode layer electrically connected to the second semiconductor layer; and a first insulating layer interposed between the first semiconductor layer and the second semiconductor layer in a second region adjacent to the first region toward the second electrode layer.

Tunneling field effect transistor

A plurality of bandpass filters () are arranged side by side in a row on a fixed surface () of a glass block () and fixed using an adhesive (). Each bandpass filter () includes a coating film () for transmitting or reflecting light depending on a wavelength. Each bandpass filter () includes a first surface () fixed to the fixed surface (), and a second surface () opposite to the first surface () and having a width larger than that of the first surface (). Opposing side surfaces of the adjacent bandpass filters () include a first portion () on the first surface () side and a second portion () on the second surface () side. A spacing between the first portions () of the adjacent bandpass filters () is wider than a spacing between the second portions () of the adjacent bandpass filters ().

Optical multiplexer/demultiplexer and method for manufacturing the same

A MOS optical modulator having high modulation efficiency and a method of manufacturing the same are provided. A MOS optical modulator includes: a p-type Si layer constituting an optical waveguide; a gate insulating film provided on the optical waveguide; a gate layer provided on the gate insulating film and formed of an n-type group III-V semiconductor; a first contact portion connected to the gate layer; and a second contact portion connected to the Si layer.

Metal-oxide-semiconductor (MOS) optical modulator and method of manufacturing same

There is provided a fabrication technique of a MOS structure that has a small EOT without increasing the interface trap density. More specifically, provided is a method of producing a semiconductor wafer that includes a semiconductor crystal layer, an interlayer made of an oxide, nitride, or oxynitride of a semiconductor crystal constituting the semiconductor crystal layer, and a first insulating layer made of an oxide and in which the semiconductor crystal layer, the interlayer, and the first insulating layer are arranged in the stated order. The method includes (a) forming the first insulating layer on an original semiconductor crystal layer, and (b) exposing a surface of the first insulating layer with a nitrogen plasma to nitride, oxidize, or oxynitride a part of the original semiconductor crystal layer, thereby forming the interlayer, together with the semiconductor crystal layer that is the rest of the original semiconductor crystal layer.

Method of producing semiconductor wafer, semiconductor wafer, method of producing semiconductor device and semiconductor device

A semiconductor substrate includes a substrate, an insulating layer, and a semiconductor layer. The insulating layer is over and in contact with the substrate. The insulating layer includes at least one of an amorphous metal oxide and an amorphous metal nitride. The semiconductor layer is over and in contact with the insulating layer. The semiconductor layer is formed by crystal growth.

Semiconductor substrate, field-effect transistor, integrated circuit, and method for fabricating semiconductor substrate

Provided is a semiconductor wafer including a base wafer, a first insulating layer, and a semiconductor layer. Here, the base wafer, the first insulating layer and the semiconductor layer are arranged in an order of the base wafer, the first insulating layer and the semiconductor layer, the first insulating layer is made of an amorphous metal oxide or an amorphous metal nitride, the semiconductor layer includes a first crystal layer and a second crystal layer, the first crystal layer and the second crystal layer are arranged in an order of the first crystal layer and the second crystal layer in such a manner that the first crystal layer is positioned closer to the base wafer, and the electron affinity Eof the first crystal layer is larger than the electron affinity Eof the second crystal layer.

Semiconductor wafer, field-effect transistor, method of producing semiconductor wafer, and method of producing field-effect transistor

Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of InGaAsP(0&#x3c;x1&#x2266;1, 0&#x2266;y1&#x2266;1), the second semiconductor crystal layer is made of InGaAsP(0&#x2266;x2&#x2266;1, 0&#x2266;y2&#x2266;1, y2&#x2260;y1), and the electron affinity Eof the first semiconductor crystal layer is lower than the electron affinity Eof the second semiconductor crystal layer.

Field-effect transistor, semiconductor wafer, method for producing field-effect transistor and method for producing semiconductor wafer

It is an objective of the present invention to form a favorable interface between an oxide layer and a group 3-5 compound semiconductor using a practical and simple method. Provided is a semiconductor wafer comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; and a second semiconductor layer that is formed to contact the first semiconductor layer, is a group 3-5 compound semiconductor layer that lattice matches or pseudo-lattice matches with InP, and can be selectively oxidized relative to the first semiconductor layer. Also provided is a semiconductor device comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; an oxide layer formed by selectively oxidizing, relative to the first semiconductor layer, at least a portion of a second semiconductor layer that is a group 3-5 compound formed to contact the first semiconductor layer and that lattice matches or pseudo-lattice matches with InP; and a control electrode that adds an electric field to a channel formed in the first semiconductor layer.

Semiconductor wafer, semiconductor device, and method of manufacturing a semiconductor device

A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a &#x3c;110&#x3e; direction.

Semiconductor device and manufacturing method thereof

A semiconductor device includes: a package case in which a semiconductor element is mounted, the package case having a bonding portion; a cap having a bonding portion bonded to the bonding portion of the package case so as to hermetically seal the semiconductor element; and one or more bonding/sealing wires disposed between and in contact with the bonding portion of the package case and the bonding portion of the cap such that the one or more bonding/sealing wires form a closed loop and hermetically seal the semiconductor element.

Semiconductor device

A field effect transistor comprises a source and a drain, and a channel layer of SiGeCcrystal (1&#x3e;x&#x3e;0, 1&#x3e;y&#x2267;0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.

Field effect transistor

In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90&#xb0;. A section perpendicular to the given direction is vertically and horizontally symmetrical.

Semiconductor device including multi-gate metal-insulator-semiconductor (MIS) transistor

A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.

Semiconductor device and method of manufacturing the same

A substrate used for fabricating devices thereon includes an insulating film, and a monocrystal Ge thin layer formed on the insulating film in contact therewith, the monocrystal Ge thin layer having a thickness not more than 6 nm. The monocrystal Ge thin layer has a thickness not less than 2 nm and a compressive strain.

Element fabrication substrate

Growing community of inventors

Tokyo, Japan

Shinichi Takagi