Sharp Kabushiki Kaisha Corporation

Shinichi Sato

Takuji Tanigami

Yukiharu Akiyama

Satoru Yamagata

Masanori Yoshimi

Katsuji Iguchi

Shinji Horii

Kenji Hakozaki

Masayuki Hirata

Yoshimitsu Yamauchi

Naoki Ueda

Kenichi Tanaka

Nobuyoshi Awaya

Keizo Sakiyama

Masaru Tanaka

Yasunari Hosoi

Shinobu Yamazaki

Shigeki Hayashida

Akio Kawamura

Naoyuki Shinmura

Toshiyuki Matsushima

Kenichi Azuma

Takayuki Taniguchi

Takayoshi Hashimoto

Kazuhiro Hirohama

Hideyuki Kanzawa

Satoshi Yoshimura

Kazuhiro Hata

Katsuya Hironaka

Tomohiko Tateyama

A nonvolatile semiconductor memory device include: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends. A transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage. A load circuit is connected to the variable resistive element in series having an adjustable load resistance. A voltage generation circuit applies a voltage to both ends of a serial circuit. The variable resistive element can transit between the states by adjusting a resistance of the load circuit.

Nonvolatile semiconductor memory device

In the non-volatile semiconductor memory in which an N-type source diffusion layer and an N-type drain diffusion layer are formed on a P-type well formed on a substrate: the source diffusion layer has a protrusion portion and a depressed portion on a cross section taken along a plane that includes (a) a straight line extending along a direction of extension of the source diffusion layer and (b) a normal line of the semiconductor substrate, and the source diffusion layer is formed of a series of (a) an upper-wall layer constituting the protrusion portion, (b) a lower-wall layer constituting the depressed portion, and (c) a side-wall layer between the upper-wall layer and the lower-wall layer; a silicide is formed to cover the upper-wall layer, the lower-wall layer, and the side-wall layer, and an insulating layer is formed to cover the silicide; and a distance d between (a) an interface between the insulating layer and the silicide formed on the upper-wall layer and (b) an interface between the insulating layer and the silicide formed on the lower-wall layer is 1000 &#x212b; or shorter. This structure allows (i) miniaturization of the non-volatile semiconductor memory and (ii) reduction in a resistance of the source diffusion layer of the non-volatile semiconductor memory.

Semiconductor memory

A semiconductor memory device comprises an array of memory cells each comprising a variable resistance element and a cell access transistor, and a voltage supplying means for applying the first voltage between the bit and source lines connected to the selected memory cell, the third voltage to the word line to apply the first write voltage between the two ports of the variable resistance element for shifting the resistance from the first state to the second state, and the second voltage opposite in polarity to the first voltage between the bit and source lines, the third voltage to the word line to apply the second write voltage opposite in polarity to and different in the absolute value from the first write voltage between the two ports for shifting the resistance from the second state to the first state, the voltage supplying means comprising an n-channel MOSFET and a p-channel MOSFET.

Semiconductor memory device

A semiconductor memory device comprises a array of memory cells arranged in a matrix, each memory cell connected to one end of a variable resistor element where the electric resistance is shifted from the first state to the second state by applying the first writing voltage and from the second state to the first state by applying the second writing voltage, and the source or drain of the selecting transistor. The second writing time for the second writing action of shifting the electric resistance of the variable resistor element from the second state to the first state is longer than the first writing time of shifting the same reversely. The second number of the memory cells subjected to the second writing action at once is greater than the first memory cell number subjected to the first writing action at once, and at least the second number is two or more.

A method for fabricating a semiconductor device including on a single semiconductor substrate, a first MOS transistor having a first gate insulating film of a predetermined thickness, and second and third MOS transistors sharing a second gate insulating film smaller in thickness than the first gate insulating film, the third MOS transistor being lower in threshold voltage than the second MOS transistor, the method includes the steps of: adjusting the threshold voltages of the first and third MOS transistors by first ion-implantation; and adjusting the threshold voltage of the second MOS transistor by second ion-implantation, the second ion-implantation being performed under implantation conditions different from those of the first ion-implantation.

Method for fabricating semiconductor device

A manufacturing method of a semiconductor memory device comprising the steps of: forming plural trenches in stripes in a semiconductor substrate and filling each of the trenches with an element isolation insulating film to form element isolation regions; sequentially forming a tunnel insulating film and a charge-storable film so as to cover active regions between the element isolation regions; forming an interlayer insulating film on the charge-storable film; forming plural control gates on the interlayer insulating film in a direction orthogonal to a longitudinal direction of the trenches; among source formation regions and drain formation regions alternately provided between the plural control gates, etching the element isolation insulating film in the source formation regions, using as a mask a resist film having openings in the source formation regions, to expose surfaces of the trenches; and carrying out isotropic plasma ion implantation on the source formation regions to form source diffusion layers in the surfaces of the trenches and in the active regions.

Semiconductor memory device and manufacturing method thereof

A method for manufacturing a semiconductor device comprising:

Method for manufacturing semiconductor device

The present invention provides a process for fabricating semiconductor device comprising the steps of: forming an etching-stop layer on a semiconductor substrate; patterning the etching-stop layer so that the etching-stop layer remains in a region to be an active region and is removed from a region to be a device isolation region, followed by forming a trench in the region to be the device isolation region; depositing on the semiconductor substrate an insulating film having a thickness greater than or equal to the depth of the trench; forming a resist pattern having an opening above the etching-stop layer above the active region adjacent to a device isolation region whose width is greater than or equal to a predetermined value, followed by etching the insulating film using the resist pattern as a mask; and polishing the insulating film existing on the resulting semiconductor substrate for flattening after removing the resist pattern.

Process for fabricating a semiconductor device

A process for forming a device isolation region comprising the steps of: forming a pad oxide film and a silicon nitride film on a semiconductor substrate; removing the pad oxide film and the silicon nitride film on a region for device isolation and forming a trench in the semiconductor substrate by etching using the remaining pad oxide film and silicon nitride film as an etching mask; forming a first oxide film at least on the bottom and sidewalls of the trench and below the pad oxide film under an end portion of the silicon nitride film using the silicon nitride film as a mask resistant to oxidization; forming a gap between the silicon nitride film and the semiconductor substrate by removing the first oxide film on the bottom and the sidewalls of the trench and the first oxide film and the pad oxide film below the end portion of the silicon nitride film by etching using the silicon nitride film as an etching mask; forming a second oxide film at least on the bottom and the sidewalls of the trench and in the gap using the silicon nitride film as a mask resistant to oxidization; and forming a third oxide film so as to fill the trench, thereby to form a device isolation region.

Process for forming device isolation region

A plurality of blocks of memory cell transistors are formed on the respective isolated wells. In a write stage, a predetermined write-stage well voltage is applied to the well of a selected block including the memory cell transistors to be subjected to a write operation, a bias voltage is applied to the well of each of the remaining, non-selected blocks to increase a threshold voltage of the memory cell transistors of each non-selected block, in comparison with a threshold voltage determined by the predetermined write-stage well voltage, and a voltage is applied to the control gates of the memory cell transistors of each non-selected block to reduce a difference between a potential of the floating gate of each memory cell transistor of each non-selected block and a write-stage drain voltage applied to the drain of the memory cell transistor through the associated bit line such that a source-drain leak current of each memory cell transistor in the non-selected blocks falls in a permissible range.

Nonvolatile semiconductor storage device having a plurality of blocks of

A process for manufacturing a non-volatile semiconductor memory device by forming a tunnel dielectric film, a floating gate electrode, an interlayer capacitive film and a control gate electrode successively on a semiconductor substrate includes introducing nitrogen atoms into at least one of an interface between the floating gate electrode and the interlayer capacitive film and an interface between the interlayer capacitive film and the control gate electrode.

Process for manufacturing non-volatile semiconductor memory device by

A method for manufacturing a semiconductor memory device, including the steps of: forming a plurality of stripes comprising a first floating gate material film and a ion implantation protective film, covering one longitudinal side wall of the stripes with a resist pattern; removing a given width of the other side wall of the first floating gate material film by an isotropic etching in use of the resist pattern as a mask; forming an impurity region of low concentration by implanting impurity ions of a second conductivity type into the semiconductor substrate of the first conductivity type in use of the ion implantation protective film as a mask in a tilted direction after removing the resist pattern; and forming asymmetrical impurity regions on both sides of the stripe like first floating gate material film as viewed in the cross section along the direction perpendicular to the longitudinal direction of the stripes. According to the above-mentioned method, without using a side wall spacer, a semiconductor memory device provided with asymmetrical impurity regions having precisely desired forms can be obtained.

Method for manufacturing semiconductor memory device

A non-volatile semiconductor memory device comprises a plurality of rewritable non-volatile memory cells arranged in an array and divided into a plurality of blocks, the non-volatile memory cells of each block being connected to a bit-line block by block through a bit-line voltage converter which includes a voltage conversion circuit section and a bypass circuit section, wherein when a selection voltage for writing is applied to the bit line extending through a plurality of blocks, the selection voltage is applied as a first voltage to the bit-line within a block which has been selected for writing so as to write data into the non-volatile memory cells connected to the bit-line within the block, and is applied as a second voltage having a smaller absolute value than the first voltage to the bit-line within a block which has not been selected for writing, by means of the voltage conversion circuit section, and when a voltage for reading is applied to the bit-line extending through the plurality of blocks, the voltage is directly applied to the bit line through the bypass circuit section without using the voltage conversion circuit section. According to the present invention, it is possible to prevent drain disturb effectively and to communicate to the plurality of blocks connected to the bit-line by means of the first or second voltage that the selection voltage has been applied to the bit-line for writing.

Non-volatile semiconductor memory device

A non-volatile semiconductor memory in which a plurality of flash memory cells are arranged in a matrix, each flash memory cell including source and drain regions formed on a silicon substrate, a floating gate formed on at least a part of the source and drain regions with a dielectric film provided therebetween, and a control gate formed on the floating gate with a dielectric layer provided therebetween, wherein a writing operation is performed by applying a positive voltage to the drain region and a negative voltage to the control gate and extracting electrons from the floating gate to the drain region by an FN tunnel current, a common source line for connecting the source region of the flash memory cells includes a diffusion layer formed in the silicon substrate and a silicide formed on the diffusion layer, and impurity concentration of the source region and the common source line are set lower than the impurity concentration of the drain region.

Non-volatile semiconductor memory

In the nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix of the present invention, the memory cell array includes: a semiconductor substrate; a tunnel oxide film formed on the semiconductor substrate; floating gates formed on the tunnel oxide film; first insulating films formed on the floating gates; and control gates formed on the first insulating films, wherein each of the floating gates includes a first polysilicon film and second polysilicon films, the second polysilicon films being formed on both sides of the first polysilicon film, second insulating films are formed on the tunnel oxide film between the first polysilicon films, the second insulating films having a predetermined thickness which is thinner than that of the first polysilicon films, and the second polysilicon films are formed on the second insulating films.

Growing community of inventors

Fukuyama, Japan

Shinichi Sato