Rohm Co., Ltd.

Shinichi Saitoh

Yo Yamashiro

Makoto Murata

Multiple flip-flops each latch input data at a time point of the corresponding clock signal. The i-th (i represents an integer) first logical gate generates an internal up signal which is asserted when the output of the (2&#xd7;i&#x2212;1)-th flip-flop does not match the output of the (2&#xd7;i)-th flip-flop. The j-th (j represents an integer) second logical gate generates an internal down signal which is asserted when the output of the (2&#xd7;j)-th flip-flop does not match the output of the (2&#xd7;j+1)-th flip-flop. A third logical gate generates an up signal based upon the multiple internal up signals. A fourth logical gate generates a down signal based upon the multiple internal down signals.

Clock data recovery circuit

A charge pump circuit is provided. A voltage/current conversion circuit compares a feedback voltage that corresponds to the output voltage of the charge pump circuit with a predetermined reference voltage, and generates a bias current that corresponds to the difference therebetween. An oscillator oscillates at a frequency that corresponds to the bias current. A buffer is biased by the bias current, and supplies a gate clock to the charge pump circuit based upon a clock signal output from the oscillator, thereby driving the charge pump circuit.

Control circuit and control method for charge pump circuit

A first receiving terminal and a second receiving terminal are connected to a first signal transmission line and a second signal transmission line, respectively, and receive the input of transmission signals. A first resistor and a second resistor convert current signals contained in the transmission signals into voltage. A comparator inputs the respective voltages converted by the first and the second resistor, and outputs, as an output signal, a voltage corresponding to a difference between their voltages. A first transistor connected to an end of the first resistor and a second transistor connected to an end of the second resistor reduce the variation in a transmission voltage signal due to the variation in the current signals contained in the transmission signals. A third transistor connected to the other end of the first resistor causes to drop power-supply voltage so as to generate a control signal. The control signal is turned into a gate voltage of the second transistor in a crosswise manner. A fourth transistor connected to the other end of the second resistor operates in the similar manner to the third transistor.

Growing community of inventors

Kyoto, Japan

Shinichi Saitoh