National Institute of Advanced Industrial Science and Technology

Shinichi Ouchi

Meishoku Masahara

Yongxun Liu

Kazuhiko Endo

Takashi Matsukawa

Kunihiro Sakamoto

Hiroyuki Ota

Tetsuji Yasuda

Hanpei Koike

Toshihiro Katashita

Tatsuro Maeda

Yohei Hori

Koichi Fukuda

Yasuhiro Ogasahara

Toshifumi Irisawa

Hiroshi Fuketa

A computing system capable of obtaining a calculation speed exceeding that of 16-bit floating point processing while maintaining accuracy of calculation results. A computing system includes a parameter server, a communication path and a worker. The parameter server has a storage unit that stores a parameter value of a training target model, and a first conversion unit that converts the parameter value into data represented by a floating point number with 10 bits or less. The communication path transmits the data transmitted and received between the parameter server and the worker. The worker has a processing unit that computes a product and a sum of the data. The parameter server further has a second conversion unit that converts the data with 10 bits or less received from the worker into an updating difference, and an updating unit that updates the parameter value on the basis of the updating difference.

Computing system for performing efficient machine learning processing

A semiconductor deviceof the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits, andhaving a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.

Semiconductor device including circuit having security function

There is provided an operational amplifier which is operable as well when an operating voltage decreases without creating a range where a circuit would not operate or reducing circuit gain. High-pass filters-provide output signals therefrom to bias-set input nodes of differential amplifiers Gm-Gmto a potential within a common-mode range in which the respective differential amplifiers Gm-Gmare operable. In this manner, the respective differential amplifiers Gm-Gmcan be operated effectively regardless of the possible decrease in a supply voltage, enabling normal amplifying operation. In addition, reduction in gain due to the reduced operational voltage is avoided. Therefore, it is preferably applicable to the application where digital and analog circuits are loaded together on the same IC chip. When a high-pass filter is required at each input side of two- or more-stage differential amplifiers, a phase compensation method utilizing multiple paths is provided for a lower range of a phase margin created at the low frequency side, enabling normal amplitude operation.

Operational amplifier

An SRAM cell includes six four-terminal double gate FETs formed on four semiconductor thin film plates, in which first and third FETs, fourth and fifth FETs, third and fourth FETs, and second and sixth FETs neighbor each other and logic signal input gates thereof are formed on facing side surfaces of respective semiconductor thin film plates; the second and sixth FETs sandwich second and third plates; the threshold voltage control gates of the second, third, fourth, and sixth FETs are connected in common to a first bias wiring; threshold voltage control gates of the first and fifth FETs are connected in common to a second bias wiring; and the word line and the first and second bias wirings are arranged in a direction perpendicular to the alignment direction of the first to the fourth plates.

SRAM cell and SRAM device

A SRAM device which can set a threshold voltage of a selection transistor appropriate for all the cells on an SRAM array is disclosed. The SRAM device uses a field effect transistor as the selection transistor. The field effect transistor includes a gate to drive the transistor and a terminal to control a threshold voltage, which are electrically separated from each other. The SRAM device also includes a circuit which, in a reading operation, gradually increases a voltage supplied to the terminal at the start of the reading to control the threshold of the selection transistor.

SRAM device capable of independently controlling a double-gate selection transistor for maintaining an optimal read margin and read speed

A manufacturing method of the nano-wire field effect transistor, comprising steps of preparing an SOI substrate having a (100) surface orientation; processing a silicon crystal layer comprising the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal layer by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other so as to face along the ridge lines of the triangular columnar members; and processing the two triangular columnar members into a circular columnar member configuring a nano-wire by hydrogen annealing or thermal oxidation.

Nano-wire field effect transistor, method for manufacturing the transistor, and integrated circuit including the transistor

Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor.

An SRAM device uses a four-terminal double gate field effect transistor as a selection transistor, wherein the four-terminal double gate field effect transistor comprises a gate which drives the transistor and a gate which controls a threshold voltage, which are electrically separated from each other, on both surfaces of a standing semiconductor thin plate, and wherein a voltage used to reduce a threshold voltage is input to the gate which controls the threshold voltage of the selection transistor during a writing operation than during a reading operation. The SRAM device which can increase both the read and write margins is provided.

SRAM device

There is provided a circuit to make a bias for adjusting a threshold voltage of MOS devices available in a wide range, to extend the amplitude range of the input voltage range of a semiconductor differential amplifier from a power supply potential to a ground potential, and automatically to ensure an operation of a differential pair in the saturation region as rejecting the common-mode signal in the entire voltage range. The semiconductor differential amplifier is configured by the first gates of two four-terminal fin type FETs serving as an input terminal of differential pair, and in that the second gates of the four-terminal fin type FETs interconnected with each other, wherein a signal decreasing monotonously along with the increase in the input common-mode component is input.

Semiconductor differential amplifier

An SRAM device including a memory cell, the memory cell having two access transistors connected to a word line, and a flip-flop circuit having complementary transistors, the transistor being a field effect transistor having a standing semiconductor thin plate, a logic signal input gate and a bias voltage input gate, the gates sandwiching the semiconductor thin plate and being electrically separated from each other, a first bias voltage is applied to bias voltage input gates of the transistors of the memory cells in a row including a memory cell being accessed for reading or writing, and a second bias voltage is applied to the bias voltage input gates of the transistors of the memory cells in a row including a memory cell under memory holding operation.

A static random access memory (SRAM) cell includes a first to a fourth semiconductor thin plate that are provided on a substrate and are arranged parallel to each other. On respective semiconductor thin plates, there is formed a first four-terminal double-gate field effect transistor (FET) with a first conductivity type, a second and a third four-terminal double-gate FET which are connected in series with each other and have a second conductivity type, a fourth and a fifth four-terminal double-gate FET which are connected in series with each other and have the second conductivity type, and a sixth four-terminal double-gate FET with the first conductivity type. The third and the fourth four-terminal double-gate FETs form select transistors, and the first, second, fifth and sixth four-terminal double-gate FETs form a complementary metal-oxide-semiconductor (CMOS) inverter.

A field-effect transistor comprising a movable gate electrode that suppresses a leakage current from the gate electrode, and has a large current drivability and a low leakage current between a source and a drain. The field-effect transistor comprises: an insulating substrate; a semiconductor layer of triangle cross-sectional shape formed on the insulating substrate, having a gate insulation film on a surface, and forming a channel in a lateral direction; fixed electrodes that are arranged adjacent to both sides of the semiconductor layer and in parallel to the semiconductor layer, each of the electrodes having an insulation film on a surface; a source/drain formed at the end part of the semiconductor layer; and the movable gate electrode formed above the semiconductor layer and the fixed electrodes with a gap.

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Tsukuba, Japan

Shinichi Ouchi