Mitsubishi Electric Corporation

Shinichi Miwa

Yoshinobu Sasaki

Naoki Kosaka

Shohei Imai

Kazuya Yamamoto

Koji Yamanaka

Atsushi Okamura

Toshiyuki Oishi

Hiroshi Otsuka

Yoshihiro Tsukahara

Kenichi Horiguchi

Ko Kanaya

Yutaro Yamaguchi

Takaaki Yoshioka

Masaharu Hattori

Kunihiro Sato

Kenichiro Chomei

Kei Fukunaga

This semiconductor device is provided with a device substrate in which a semiconductor circuit including two high frequency amplifiers; a cap substrate and a sealing frame of a conductor which forms and air-tightly seals space surrounding an area, in which the semiconductor circuit is formed, between the device substrate and the cap substrate, wherein the sealing frame is configured as a line of a 90-degree hybrid circuit or a line of a rat-race circuit.

Semiconductor device comprising sealing frame configured as a conductor

An amplifier includes a transistor chip including a plurality of transistor cells, a gate pad, and a drain pad, a matching substrate having a surface on which a metal pattern is formed, a terminal with a width larger than a width of the transistor chip and than a width of the matching substrate, a plurality of terminal wires connecting the terminal to the metal pattern, and a plurality of chip wires connecting the metal pattern to the transistor chip. Inter-wire distances of portions of the plurality of terminal wires connected to the metal pattern are larger than inter-wire distances between portions of the plurality of terminal wires connected to the terminal.

Amplifier

A semiconductor device includes: a depletion-type field-effect transistor including a gate terminal, a drain terminal and a source terminal; a group III-V heterojunction bipolar transistor including a base terminal, an emitter terminal electrically connected to the gate terminal and a collector terminal connected to same potential as that of the source terminal; a first resistor connected between the base terminal and the emitter terminal; and a second resistor connected between the base terminal and the collector terminal.

FET gate stabilizing circuit

An amplifier includes a package, a transistor chip having a gate pad and a drain pad formed elongately, the transistor chip being provided in the package, and a plurality of drain bonding wires connected to the drain pad, wherein the plurality of drain bonding wires include a first outer-most bonding wire connected to one of two end portions of the drain pad, a second outer-most bonding wire connected to the other of the two end portions of the drain pad, and an intermediate bonding wire interposed between the first outer-most bonding wire and the second outer-most bonding wire, each of the plurality of drain bonding wires is longer than 1 mm, and the first outer-most bonding wire and the second outer-most bonding wire have loop heights larger than a loop height that the intermediate bonding wire has.

Amplifier package with multiple drain bonding wires

A high frequency device includes a base plate having a main surface, a dielectric on the main surface, along a first side of the base plate, a signal line on the dielectric and extending from the first side toward a central portion of the main surface, an island pattern of a metal on the dielectric, a metal frame having a contact portion contacting the main surface and a bridge portion on the signal line and the island pattern, together enclosing the central portion, a lead frame connected to an outside signal line of the signal line and which is located outside the metal frame, a semiconductor chip secured to the central portion, and a wire connecting the semiconductor chip to an inside signal line of the signal line and which is enclosed within the metal frame.

High frequency device

An amplifier includes a transistor chip, a matching chip with a capacitor group having multiple MIM capacitors, each of the MIM capacitors including a lower electrode, a dielectric, and an upper electrode, a bonding wire that electrically connects the transistor chip to the upper electrode of any one of the MIM capacitors of the capacitor group and transmits a high-frequency signal, and a case that accommodates the transistor chip and the matching chip. The lower electrodes of the MIM capacitors are grounded, and capacitance values of each of the MIM capacitors of the capacitor group are different from each other.

A power amplifier includes a semiconductor substrate including transistor cells, a drain electrode for the transistor cells located on the semiconductor substrate, a drain pad located on the semiconductor substrate and connected to the drain electrode, an ion-implanted resistance located in the semiconductor substrate and extending along and in contact with the drain pad, a floating electrode located on the semiconductor substrate and in contact with the ion-implanted resistance, and an output matching circuit located outside the semiconductor substrate. The power amplifier further includes a wire connecting the drain pad to the output matching circuit.

Power amplifier

A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.

Transistor characteristic calculation apparatus using large signal equivalent circuit model

A high frequency power amplifier includes an FET chip, a wire connected at a first end to the FET chip, an input-side matching circuit substrate, a resistive element on the input-side matching circuit substrate and connected in series with the FET chip, a transmission portion of a conductive material on the input-side matching circuit substrate, in contact with one end of the resistive element, and connected to an input electrode, a wire connection portion of a conductive material on the input-side matching circuit substrate, in contact with a second end of the resistive element, and connected to a second end of the wire, and a shorting portion of a conductive material having a smaller width than the resistive element and on the resistive element, connecting the transmission portion to the wire connection portion.

Growing community of inventors

Tokyo, Japan

Shinichi Miwa