Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Shinichi Marui

Minoru Okamoto

Toshihisa Nakano

Natsume Matsuzaki

Kazuhiro Okabayashi

Katsuhiko Ueda

Tatsuya Tetsukawa

Atsuhiro Mori

The present invention provides an apparatus for securely acquiring a circuit configuration information set corresponding to a new cryptosystem without increasing the number of reconfigurable circuits. A content playback apparatus includes an FPGA that is reconfigurable. The content playback apparatus stores a decryption circuit program that shows the structure of a decryption circuit that executes decryption in accordance with a prescribed cryptosystem. The FPGA is reconfigured in accordance with the program to configure the decryption circuit. The playback apparatus acquires, from outside, an encrypted file that has been generated by encrypting a file including a decryption circuit program corresponding to the new cryptosystem in accordance with the prescribed cryptosystem, and decrypts the encrypted file by the decryption circuit.

Circuit building device

An information processing apparatus includes a reconfigurable unit in which a circuit is reconfigured. A generation unit generates design data for the circuit configured by the reconfigurable unit and reduces the amount of design data to be held by a design data storage unit.

Circuit updating system

The present invention provides an apparatus for securely acquire a circuit configuration information set corresponding to a new cryptosystem without increasing the number of reconfigurable circuits. A content playback apparatusincludes an FPGAthat is reconfigurable. The content playback apparatusstores a decryption circuit program that shows the structure of a decryption circuit that executes decryption in accordance with a prescribed cryptosystem. The FPGA is reconfigured in accordance with the program to configure the decryption circuit. The playback apparatusacquires, from outside, an encrypted file that has been generated by encrypting a file including a decryption circuit program corresponding to the new cryptosystem in accordance with the prescribed cryptosystem, and decrypts the encrypted file by the decryption circuit.

Information security device

A semiconductor integrated circuit () according to the present invention includes a plurality of reconfigurable cores () arranged separately from each other in a matrix, and a first group of register circuits () formed between a first and second reconfigurable cores included in the reconfigurable cores (). Each of the reconfigurable cores () operates synchronously with clock signals and has a logic reconfiguration function, and includes a plurality of logic elements () that implements predetermined logic and programmable wiring (and) that interconnects the plurality of logic elements (). The first group of register circuits () temporarily holds output from the first reconfigurable core and transfers the output to the second reconfigurable core.

Semiconductor integrated circuit, program transformation apparatus, and mapping apparatus

A plurality of logic element groups LEGto LEGrespectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEGand LEG, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element. The logic element groups LEGto LEGare therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.

Reconfigurable semiconductor integrated circuit and processing assignment method for the same

The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced. In a programmable logic deviceformed from programmable logical elements, there are provided first logical elementsand second logical elementshaving the same logic as the first logical elementsbut having an upper limit of operating speed designed to be lower than that of the first logical elements

Programmable logic device and method for designing the same

A first processor, a second processor, a memory and a clock supply unit are integrated together on a single chip. The first processor operates synchronously with a first internal clock signal. The second processor operates synchronously with a second internal clock signal. The memory operates synchronously with a third internal clock signal. The clock supply unit generates three clock signals, which are in phase with each other, from an external clock signal and supplies those clock signals as the first, second and third internal clock signals. The first and second processors share the memory via a data bus. Each of the processors has an internal reset signal.

Apparatus for controlling and supplying in phase clock signals to components of an integrated circuit with a multiprocessor architecture

In a circuit blockto be an object of power-off, voltage detecting circuitsandare disposed near power supply terminalsand, respectively, and voltage detecting circuitsandare disposed at given positions far from the terminalsand, respectively, on power linesandof two electric-supply systems. The voltage detecting circuits are each made of MOS transistors only. At turning on the power from a power supply circuitagain, after all the voltage detecting circuits have detected arrival of power-supply voltages at a predetermined potential, a reset signal generating circuitstops the input of a reset signal to the circuit blockAccordingly, since the reset state is stopped after the arrival of the power-supply voltages at the predetermined voltage, a semiconductor integrated circuit is initialized normally. This provides a semiconductor integrated circuit capable of generating a power-on reset signal appropriately.

Semiconductor integrated circuit and its reset method

Each of processors has an input/output port provided with a data terminal for transmitting and receiving address information and data to be transferred, a mode terminal for transmitting and receiving a mode signal indicative of whether a signal at the data terminal represents the address information or the data to be transmitted, a read/write terminal for transmitting and receiving a read/write signal indicative of a timing for each of the signal at the data terminal and a signal at the mode terminal, an input buffer and an output buffer each connected to the data terminal, a data memory pointer connected to the internal data memory, and a control circuit connected to the mode terminal and to the read/write terminal.

Interface for multi-processor

A moving picture encoding decoding processing apparatus for detecting a motion vector by forming the image data of the search area for motion vector with small capacity of memory rapidly and efficiently. A moving picture encoding decoding processing apparatus detects the macroblock number by a macroblock counter. A macroblock recognition part recognizes whether the search area for the motion vector of the macroblock is extending over the frame image area or not based on the position of the macroblock in the frame image. A macroblock recognition part generates an extrapolation pattern signal which indicates the pattern of the extrapolation for the inputted macroblock. If the whole search area is within the frame area, image data formed on a frame memory are used. If the search area extends beyond the frame area, image data formed on a prediction memory are used. A control unit 1 includes an image data transmission means. Image data of the current processing macroblock data and surrounding data existing on the frame memory are transferred from the frame memory to the prediction memory . The prediction memory includes an image data extrapolation means. The image data extrapolation means performs the extrapolation by specifying row address and column address necessary for the extrapolation based on the transmitted image data from the frame memory and the extrapolation pattern signal.

Moving picture encoding decoding processing apparatus

A shift operation unit includes: a shift means for shifting data in accordance with a shift count and outputting the most significant part bit data, intermediate bit data, and least significant part bit data; first selection means coupled to an output of the shift means, for selecting one of the most significant part bit data and the least significant part bit data in accordance with a shift direction; first storage means coupled to an output of the first selection means, for storing data selected by the first selection means; operation means coupled to an output of the shift means and an output of the first storage means, for operating the intermediate bit data and the data stored in the first storage means and outputting an operation result; and second storage means coupled to an output of the operation means, for storing the operation result. A shift operation method is also provided.

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Osaka, Japan

Shinichi Marui