Kabushiki Kaisha Toshiba

Shinichi Kimoto

Ryosuke Iijima

Katsuhisa Tanaka

Shinsuke Harada

Shinya Kyogoku

A semiconductor device of embodiments includes: a silicon carbide layer including a trench, a n-type first SiC region, a p-type second SiC region on the first SiC region, a n-type third SiC region on the second SiC region, a fourth SiC region of p-type between the first trench and the first SiC region, and a fifth SiC region electrically connecting the second SiC region and the fourth SiC region; and a gate electrode in the trench. The first trench has a first region extending in a first direction, a second region continuous with the first region, and a third region continuous with the second region and extending in the first direction. The second width of the second region in the second direction is larger than the first width of the first region in the second direction. The fifth SiC region is disposed in the second direction of the second region.

Semiconductor device, semiconductor device manufacturing method, inverter circuit, drive device, vehicle, and elevator

A semiconductor device according to an embodiment includes: a silicon carbide layer having a first plane parallel to a first direction and a second direction orthogonal to the first direction, and a second plane facing the first plane, the silicon carbide layer including a first trench and a second trench extending in the first direction; a gate electrode in the first trench and the second trench; a gate insulating layer; a gate wiring extending in the second direction, intersecting with the first trench and the second trench, connected to the gate electrode; a first electrode; a second electrode; and an interlayer insulating layer provided between the gate electrode and the first electrode. Neither the gate electrode nor the gate wiring is present between an end of the first trench in the first direction and the interlayer insulating layer.

Semiconductor device, inverter circuit, drive device, vehicle, and elevator

A semiconductor device of an embodiment includes a first trench extending in a first direction in a silicon carbide layer; a second trench and a third trench adjacent to each other in the first direction; a first silicon carbide region of n type; a second silicon carbide region of p type on the first silicon carbide region; a third silicon carbide region of n type on the second silicon carbide region; a fourth silicon carbide region of p type between the first silicon carbide region and the second trench; a fifth silicon carbide region of p type between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode, part of which is in the second trench, the first electrode contacting the first silicon carbide region between the fourth silicon carbide region and the fifth silicon carbide region; and a second electrode.

A semiconductor device of an embodiment includes: a first trench located in a silicon carbide layer extending in a first direction; a second trench and a third trench adjacent to each other in the first direction; n type first silicon carbide region; p type second silicon carbide region on the first silicon carbide region; n type third silicon carbide region on the second silicon carbide region; p type fourth silicon carbide region between the first silicon carbide region and the second trench; p type fifth silicon carbide region between the first silicon carbide region and the third trench; p type sixth silicon carbide region shallower than the second trench between the second trench and the third trench and having a p type impurity concentration higher than that of the second silicon carbide region; a gate electrode in the first trench; a first electrode, and a second electrode.

A semiconductor device according to an embodiment includes: a silicon carbide layer having a first plane, a second plane facing the first plane, a first trench, a second trench, an n-type first silicon carbide region, a p-type second silicon carbide region between the first silicon carbide region and the first plane, an n-type third silicon carbide region between the second silicon carbide region and the first plane, and a p-type fourth silicon carbide region between the second trench and the first silicon carbide region; a gate electrode being located in the first trench; a gate insulating layer; a first electrode, a portion of the first electrode being located in the second trench; a second electrode; and an interlayer insulating layer being located between the gate electrode and the first electrode, in which an interface between the first electrode and the interlayer insulating layer is located in the first trench.

Semiconductor device, method of manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator

A semiconductor device according to an embodiment includes: a SiC layer having a first plane, a second plane, a first trench located on a first plane side, an n-type first SiC region, a p-type second SiC region between the first SiC region and the first plane, an n-type third SiC region between the second SiC region and the first plane, and a p-type fourth SiC region between the first SiC region and the first plane, at least a portion of the fourth SiC region located in the second SiC region, the fourth SiC region having a higher p-type impurity concentration than the second SiC region; a gate electrode in the first trench; a first electrode located on the first plane side; and a second electrode located on a second plane side. A depth of the fourth SiC region increases with distance from the first trench.

A semiconductor device according to an embodiment includes: a SiC layer having a first plane and a second plane facing the first plane, the SiC layer including a first trench on a first plane side, an n-type first SiC region, a p-type second SiC region, an n-type third SiC region located in this order from the second plane to the first plane, a p-type fourth SiC region between the first SiC region and the first trench, a fifth SiC region between the first SiC region and the first plane, and a sixth SiC region between the fourth SiC region and the fifth SiC region, and the sixth SiC region having an n-type impurity concentration higher than an n-type impurity concentration of the first SiC region; a gate electrode in the first trench; a first electrode on the first plane side; and a second electrode on a second plane side.

Growing community of inventors

Tsukuba, Japan

Shinichi Kimoto