Fujitsu Corporation

Kyushu Fujitsu Electronics Limited

Shinichi Inoue

Hiroshi Tokunaga

Nobuo Toyokura

Masaichi Shinoda

Hajime Ishikawa

Hirotaka Kashiwabara

Tatsuro Nakahara

Mamoru Shirai

A phase-locked loop (PLL) circuit performing a fractional division includes a phase comparator circuit, a phase difference signal modulation circuit, and an oscillator circuit. The phase comparator circuit compares phases of two signals and outputs first and second phase difference signals. The phase difference signal modulation circuit modulates the second phase difference signals into third phase difference signals, and the oscillator circuit oscillates based on the first and third signals.

PLL circuit and frequency division method reducing spurious noise

A first inverter logic element, a second inverter logic element, and a third inverter logic element constitute a loop circuit, and a first transistor, a second transistor, and a third transistor are connected between an output of the third inverter logic element and an input of the first inverter logic element. An output signal is taken out from an output of the second inverter logic element, and an oscillation frequency is regulated by the first transistor, the second transistor and the third transistor. Consequently, in a voltage controlled oscillator of the present invention, the number of loop circuits and transistors for regulating the oscillation frequency can be decreased, so that a simulation process can be simplified and required characteristics of the oscillation frequency can be easily obtained.

Voltage controlled oscillator using control transistors in a loop formed

A metal layer of a metal-insulator-semiconductor type semiconductor device, e.g., a metal electrode on an oxide layer covering a semiconductor substrate of an MOS diode or an MOS FET, contains at least one cation-trapping element. The semiconductor substrate with the metal layer and the oxide layer is heated at an elevated temperature to diffuse some of the ions responsible for the cation-trapping element out of the metal layer and into the upper part of the oxide layer. The metal and oxide layers promote the surface passivation of the semiconductor device.

Method for producing MOS semiconductor device

A magnetically controlled switching device having a magnetic shunt plate with many terminals arrayed along the peripheral portions thereof, a plurality of coil forms located at the crosspoints of a matrix consisting of X and Y coordinates on a plane surrounded by the terminals on the magnetic shunt plate, an X coil control line wound on each of the coil forms in the row in the X direction in an alternately reversed manner, both ends of the X coil line being connected to corresponding terminals located along the X direction, a Y coil control line wound on each of the coil forms in the column in the Y direction in an alternately reversed manner, both ends of the Y coil control line being connected to corresponding terminals located along the Y direction, reed switches accommodated in each of the coil forms, contact points of the reed switches corresponding to the magnetic shunt plate, and the reed switches being connected to a plurality of matrix crosspoints consisting of multiple connection wires in the directions X and Y, which are arrayed on both the front and back surfaces of the magnetic shunt plate. A relay terminal plate having a plurality of pairs of coil relay terminals is provided at a central portion of the magnetic shunt plate to divide the coil forms into two groups, such that at least two independent matrices are formed on the magnetic shunt plate.

Growing community of inventors

Kawasaki, Japan

Shinichi Inoue