Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Systems Co., Ltd.

Other

Hitachi Vsli Engineering Corp.

Shinichi Ikenaga

Masashi Horiguchi

Kazuhiko Kajigaya

Akira Endo

Ryoichi Hori

Takashi Yamazaki

Kazuyoshi Oshima

Kazuyuki Miyazawa

Jun Etoh

Yuji Sakai

Hiroshi Yoshioka

Yasunori Yamaguchi

Tetsurou Matsumoto

Makoto Morino

Yasuhiro Kasama

Shinji Udo

Eiji Miyamoto

Mitsuhiro Takano

Sinichi Miyatake

Manabu Tsunozaki

Jiro Sawada

Hirokazu Saito

Atsushi Kumata

Masakazu Aoki

Yoshinobu Nakagome

Katsuhiro Shimohigashi

Kiyoo Itoh

Toshiaki Masuhara

Toshio Sasaki

Hideo Nakamura

Osamu Minato

Toshifumi Ozaki

Masahi Horiguchi

A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

Semiconductor memory device and defect remedying method thereof

A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. This structure in which the peripheral circuits are arranged at the center portion of the chip permits the longest signal transition paths to be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. A benefit of this structure in which the peripheral circuits are arranged at the center portion of the chip, is that the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Semiconductor device formed in a rectangle region on a semiconductor substrate including a voltage generating circuit

Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Semiconductor memory device having zigzag bonding pad arrangement

A highly integrated memory features increased reading speed and writing speed. A sense circuit for this memory including a memory cell array having a plurality of memory cells each of which including at least one insulated gate field effect transistor, and a plurality of data lines to which the memory cells are connected. The memory also includes an address selection mechanism which is capable of selecting a memory cell out of a plurality of memory cells and connecting it to the data line. A sense amplifier a mechanism which is connected to the data line and amplifies a voltage according to the data of a memory cell. A common line (input/output line) is connected to the data lines, via a column switch, where the selection depends upon a column address. A main amplifier is connected to the common line (input/output line), and has at least a mechanism for stabilizing the voltage of the common line (input/output line) and an amplifying mechanism.

Sense circuit and semiconductor memory having a current-voltage

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Koganei, Japan

Shinichi Ikenaga