Oki Electric Industry Co., Ltd.

Shinichi Fukuzako

Tetsuya Tanabe

Shinichi Satoh

Shuichi Hashidate

Kenji Kokuda

Junji Kashiwada

A display device comprises a plurality of first to fourth switching elements. On the basis of control signals from the drive control circuit, the common line is brought to the selected state when the common line is connected to the low-voltage portion for common lines by turning on the first switching element and turning off the second switching element; the common line is brought to the non-selected state when the common line is brought to the high-impedance state by turning off both the first and second switching elements; the data line is brought to the selected state when the data line is connected to the high-voltage portion for data lines by turning off the third switching element and turning on the fourth switching element; and the data line is brought to the non-selected state when the data line is connected to the low-voltage portion for data lines by turning on the third switching element and turning off the fourth switching element.

Matrix display device, matrix display driving method, and matrix display driver circuit

A drive circuit includes an input node for receiving data and an output node. The drive circuit also includes a first MOS transistor of a first conductivity type and a second MOS transistor of the first conductivity type. The first MOS transistor has a source, a drain connected to the output node, and a gate connected to the input node. The second MOS transistor has a source, a drain connected to the source of the first MOS transistor, and a gate supplied with a predetermined potential level. The drive circuit also includes a resistance connected between the source of the second MOS transistor and a source node supplied with a source potential level.

Drive circuit for driving a current-driven display unit

Drive circuit for driving a current driven display unit

A semiconductor integrated circuit is provided that achieves a lesser degree of inconsistency in the delay time of clock signals that are internally provided. An input clock signal distributed via an input clock supply path is provided to individual timing adjustments circuits. The timing adjustment circuits are each constituted by providing a wiring pattern having serial resistors and gaps in a circuit correction area. The wiring pattern of the semiconductor integrated circuit is corrected by employing a focused ion beam apparatus to achieve an adjustment so that internal input clock signals at the same phase are obtained from the individual timing adjustment circuits. Using the wiring pattern having undergone the adjustment, a semiconductor integrated circuit is manufactured as a product.

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Kanagawa, Japan

Shinichi Fukuzako