Hitachi, Ltd.

Renesas Technology Corp.

Other

Hitachi Ulsi Systems Co., Ltd.

Renesas Electronics Corporation

Shinichi Fukada

Naotaka Hashimoto

Hiromi Abe

Hiroshi Momiji

Masayuki Suzuki

Masanori Kojima

Nobuyoshi Kobayashi

Shuji Ikeda

Shinji Nishihara

Hideo Aoki

Takayuki Oshima

Kazuo Nojiri

Takashi Yunogami

Shoji Hotta

Yoshitaka Nakamura

Yoshifumi Kawamoto

Takuya Fukuda

Masayoshi Saito

Masashi Horiguchi

Norio Hasegawa

Yoshitaka Tadaki

Makoto Ohkura

Aritoshi Sugimoto

Kunio Miyazaki

Jin Onuki

Yasushi Koubuchi

Makoto Ogasawara

Kiyonori Ohyu

Tatsuo Itagaki

Masayuki A Suzuki

Haruo Akahoshi

Takeyuki Itabashi

Kinya Kobayashi

Jun Sugiura

Masayasu Nihei

Akihiro Sano

Toshio Haba

Katsuhiko Shiota

Motoo Suwa

Katuhiko Shiota

Genji Taki

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Method of fabricating semiconductor integrated circuit device

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and' a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Method of fabricating semiconductor device

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Method for fabricating semiconductor device

Method of fabricating semiconductor integrated circuit device with 99.99 wt% cobalt

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and' a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Insulating films through (of which insulating films are silicon nitride films and insulating films are silicon oxide films) are sequentially formed on the wires of the fourth wiring layer and groove pattern is transferred into the insulating film by means of photolithography. An anti-reflection film is formed to fill the grooves of the insulating film and then a resist film carrying a hole pattern is formed. The films are subjected to an etching operation in the presence of the resist film to transfer the hole pattern into the insulating films and part of the insulating film . Subsequently, the resist film and the anti-reflection film are removed and the groove pattern and the hole pattern are transferred respectively into the insulating film and the insulating film by using the insulating film as mask.

Semiconductor device and method of manufacturing the same

The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

Dynamic random access memory including a logic circuit and an improved storage capacitor arrangement

Process for producing semiconductor integrated circuit device

Growing community of inventors

Hino, Japan

Shinichi Fukada