Samsung Electronics Co., Ltd.

Shinhwan Kang

Kohji Kanamori

Jeehoon Han

Youngwoo Park

Haemin Lee

Changhyun Lee

Jaeduk Lee

Younghwan Son

Jaesung Sim

Seogoo Kang

Jaeryong Sim

Sanghun Chun

Heonkyu Lee

Yunghwan Son

Jihwan Kim

Jongwon Kim

Sunil Shim

Junghoon Park

Jisung Cheon

Jinsoo Lim

Donghwan Kim

Byunggon Park

Jung-Hwan Park

Hyojoon Ryu

Jesuk Moon

Kiyoon Kang

Youngji Noh

Sunghan Cho

A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy vertical structure are contacting the pattern structure, and wherein at least one of the dummy vertical structures extend further into the pattern structure than the memory vertical structure in a downward direction.

Semiconductor device and electronic system

Disclosed is a three-dimensional semiconductor device including a horizontal semiconductor layer including a plurality of well regions having a first conductivity and a separation impurity region having a second conductivity, and a plurality of cell array structures provided on the well regions of the horizontal semiconductor layer, respectively. The separation impurity region is between and in contact with the well regions. Each of the cell array structures comprises a stack structure including a plurality of stacked electrodes in a vertical direction to a top surface of the horizontal semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to a corresponding well region.

Three-dimensional semiconductor device

A semiconductor memory device includes a first substrate; active or passive circuits on the first substrate; a second substrate above the active or passive circuits; gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction; channel structures penetrating through the gate electrodes and extending in the first direction, and each including a channel layer; separation regions penetrating through the gate electrodes and extending in a second direction; a through-contact plug extending through the second substrate in the first direction and electrically connecting the gate electrodes and the active or passive circuits to each other; and a barrier structure spaced apart from the through-contact plug and surrounding the through-contact plug and having first regions each having a first width, and second regions each having a second width greater than the first width.

Semiconductor devices and data storage systems including the same

Disclosed are three-dimensional semiconductor memory devices, electronic systems including the same, and methods of fabricating the same. The three-dimensional semiconductor memory device includes a substrate including a cell array region and an extension region, a peripheral circuit structure including peripheral transistors on the substrate, a stack structure including interlayer dielectric layers and gate electrodes that are alternately stacked on the peripheral circuit structure, contacts that penetrate the stack structure on the extension region and are electrically connected with the peripheral transistors and include a protruding part contacting a sidewall of one of the gate electrodes and a vertical part penetrating the stack structure, and dielectric patterns between the vertical part and respective sidewalls of the gate electrodes. Top and bottom surfaces of each of the dielectric patterns are respectively in contact with adjacent ones of the interlayer dielectric layers.

Three-dimensional semiconductor memory devices, methods of fabricating the same, and electronic systems including the same

A vertical memory device including gate electrodes on a substrate, the gate electrodes being spaced apart in a first direction and stacked in a staircase arrangement; a channel extending through the gate electrodes in the first direction; a first contact plug extending through a pad of a first gate electrode to contact an upper surface of the first gate electrode, the first contact plug extending through a portion of a second gate electrode, and the second gate electrode being adjacent to the first gate electrode; a first spacer between the first contact plug and sidewalls of the first gate electrode and the second gate electrode facing the first contact plug, the first spacer electrically insulating the first contact plug from the second gate electrode; and a first burying pattern contacting bottom surfaces of the first contact plug and the first spacer, the first burying pattern including an insulating material.

Vertical memory devices

A semiconductor device includes a lower structure including a peripheral circuit; a stack structure on the lower structure, extending from a memory cell array region to a stepped region, and including a gate stacked region, and an insulator stacked regions arranged in the stepped region in a first direction; a capping insulating structure on the stack structure; and separation structures passing through the gate stacked region. The stack structure includes interlayer insulating layers and horizontal layers, alternately and repeatedly stacked, the horizontal layers include gate horizontal layers and insulating horizontal layers, the gate stacked region includes the gate horizontal layers, each of the insulator stacked regions includes the insulating horizontal layers, in the stepped region, the stack structure includes a first stepped region, a connection stepped region, and a second stepped region.

Semiconductor device and electronic system including the same

A semiconductor device includes a substrate; a stack structure on the substrate and including an alternating stack of interlayer insulating layers and gate electrodes; first and second separation regions each extending through the stack structure and extending in a first direction; a first upper separation region between the first and second separation regions and extending through a portion of the stack structure; a plurality of channel structures between the first and second separation regions and extending through the stack structure; and a plurality of first vertical structures each extending through a particular one of the first and second separation regions. Each of the first and second separation regions has a first width in a second direction that is perpendicular to the first direction. Each first vertical structure has a second width in the second direction, the second width being greater than the first width.

A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.

Semiconductor device

A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

Vertical semiconductor devices

A semiconductor memory device including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first and second semiconductor layers, gate electrodes arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, and channel structures penetrating the first, second and third semiconductor layers and the gate electrodes, each respective channel structure of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film including a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, and the charge storage film including an upper cover protruding toward the outside of the respective channel structure.

Semiconductor memory devices

A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.

Growing community of inventors

Seoul, South Korea

Shinhwan Kang