Micron Technology Incorporated

Elpida Memory, Inc.

Shingo Mitsubori

Hiroki Fujisawa

Ryo Fujimaki

Kazutaka Miyano

William Chad Waldrop

Hidekazu Noguchi

Liang Chen

Yutaka Uemura

Kenji Mae

Atsuko Momma

Apparatuses for timing control in a write path are disclosed. An example apparatus includes: a clock input circuit that receives a clock signal and provides an internal clock signal; a command decoder that receives command signals and the internal clock signal, and provides an active write command signal when the command signals indicates a write operation; a write latency shifter that receives the write command signal, a latency value and a WICA value, adjusts timing of the write command signal responsive to the latency value and the WICA value, and provides a shifted write command signal; and a write DLL including a delay line that receives the shifted write command signal and provides a delayed write command signal. The write DLL provides the WICA value to set a propagation time from the clock input circuit to the write DLL to be a multiple of a period of the clock signal.

Apparatuses for timing control in write path

Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

Apparatuses and methods for a per-DRAM addressability synchronizer circuit

Embodiments of the disclosure are drawn to apparatuses and methods for controlling refresh operations. Responsive to a refresh command, or one or more pumps generated responsive to the refresh command, different banks of a memory array may perform different types of refresh operations for a pump. In some examples, the type of refresh operation performed by a bank may vary from pump to pump of a refresh operation.

Apparatuses and methods for controlling refresh operations

Apparatuses and methods for providing multiphase clocks are disclosed. An example apparatus includes a plurality of clock circuits, each configured to provide one of the multiphase clocks responsive to a respective input clock. The apparatus further includes first and second control circuits. The first control circuit receives a first one of the multiphase clocks and a reset signal provided to the plurality of clock circuits, and provides a first control signal to reset a clock circuit of the plurality of clock circuits that is based on the first one of the multiphase clocks and the reset signal. The second control circuit receives the control clock and a second one of the multiphase clocks and provides a second control signal to clock the clock circuit of the plurality of clock circuits that is based on the control clock and the second one of the multiphase clocks.

Apparatuses and methods for providing multiphase clocks

A semiconductor memory disclosed in this disclosure includes first and second memory cell arrays, a first main data line that transfers the read data read from the first memory cell array, a second main data line that transfers the read data read from the second memory cell array, a main amplifier coupled to the second main data line, and a repeater circuit coupled to the first main data line and the second main data line.

Semiconductor memory device including a repeater circuit on main data lines

The present invention efficiently decides line failure and contact failure in a semiconductor device. The semiconductor device has a plurality of bit line groups in which connection with local I/O lines is controlled by the same column selection signal line. A failure detecting circuit compares a first data group read from a first bit line group and a second data group read from a second bit line group to detect whether or not connection failure (contact failure) with the column selection signal line occurs in one of the first and second bit line groups.

Semiconductor device having bit lines and local I/O lines

To include a first level shift circuit that converts a first internal clock signal having an amplitude value of a first voltage into a second internal clock signal having an amplitude value of a second voltage, a second level shift circuit that converts a first internal data signal having the amplitude value of the first voltage into a second internal data signal having the amplitude value of the second voltage, a clock dividing circuit that generates third and fourth internal clock signals, which are complementary signals, based on the second internal clock signal, and an output circuit that outputs external data signals continuously from a data output terminal in synchronization with the third and fourth internal clock signals based on the second internal data signal. According to the present invention, because a level shift of a signal is performed before it is input to the output circuit, there occurs no skew in output data.

Growing community of inventors

Tokyo, Japan

Shingo Mitsubori