Nec Corporation

Shingo Kojima

Junichi Iwasaki

The present invention provides an input buffer circuit which prevents, when a microprocessor reads an external data bus upon bus sizing, a microprocessor from fetching an intermediate potential of the external data bus. READY terminal 3 is connected to one of a pair of input terminals of NOR gate 12 via latches 7 and 8, and lower data input terminal 4 is connected to the other input terminal of NOR gate 12. The output terminal of NOR gate 12 is connected to a data input terminal of data latch 14. SZRQ terminal 2 is connected to one of a pair of input terminals of NAND gate 10 via latches 5 and 6, and the output of latch 8 is connected to the other input terminal of NAND gate 10 via inverter 9. The output terminal of NAND gate 10 and upper data input terminal 1 are connected to input terminals of NOR gate 11, and the output terminal of NOR gate 11 is connected to an input terminal of data latch 13. Output terminals of data latches 13 and 14 serve as output terminals of the input buffer circuit.

Input buffer circuit for a microprocessor which prevents improper data

The present invention simplifies a partial multiplier selector for a multiplication circuit using the Booth Algorithm. For this purpose, a partial multiplier selector according to the present invention comprises a multiplier register to store multiplier data, a plurality of partial multiplier selecting units comprising clocked inverters which divide the multiplier data stored in the multiplier register using the multiplication start signal and sequentially fetch them and control circuits comprising latch circuits which sequentially output the multiplication start signal to the partial multiplier selecting units with a delay of one clock using the clock signal.

Partial multiplier selector for multiplication circuit

An arithmetic processing unit which speeds up arithmetic operations performed up on vectors, matrices or a vector and a matrix, and is coupled to a central processing unit. The arithmetic unit includes a program memory for storing a microprogram corresponding to a macro-instruction code fed from the central processing unit, wherein each macro-instruction is representative of an arithmetic operation. Within the arithmetic unit, operand codes are transferred from an internal register array to operand registers assigned to an augend and an addend, or a multiplicand and a multiplier for calculations carried out by an arithmetic and logic unit. The operand codes for the arithmetic operation are successively transferred to the internal register array prior to the execution of the macro-instruction codes, so that the arithmetic processing unit completes each task without the need for interruptions to receive operands.

Data processing system capable of performing vector/matrix processing

A processor includes an exception detector for receiving floating-point data on which a rounding operation is to be performed. The exception detector detects whether or not an overflow or an underflow exception occurs in floating-point data without using output floating-point data obtained by performing a rounding operation on the input floating-point data. The exception detector includes a flag indicating the type of rounding operation to be performed and an adder which unconditionally performs a rounding operation by raising a mantissa part of input floating-point data. An exponent detector evaluates an exponent part of the input floating-point data to set flags indicative of the exponent. A circuit produces overflow or underflow exception signals based on the flags and an output from the adder.

Floating-point processor provided with high-speed detector of overflow

A microprogram transfer register designation system for a microprogram controlled microprocessor which has a plurality of internal data buses such that there are previously prepared some number of source register sets each designating one source register for each of the internal buses and some number of destination register sets each designating one destination register for each of the internal buses, wherein one of the source register sets and one of the destination register sets is selected when an interregister transfer is executed. A transfer register designation field of a microcode includes at least one transfer inhibit flag for the internal buses.

Microprogram controlled microprocessor having a plurality of internal

A microprogram controlled microprocessor capable of normalizing a given data in a floating point representation includes a memory storing a microprogram, an address register for holding a microprogram start address, an operand register for holding a source operand, a temporary register for temporarily holding an operation data, a pointer for holding a code indicative of the operand register at the time of starting the microprogram and for indicating a transfer source register in a transfer operation between internal registers, and a discriminator for discriminating whether or not an input source operand is a normalized number. The microprocessor operates on the basis of the microprogram to execute a given operation to the input source operand while causing the discriminator to discriminate whether or not the input source operand is a normalized number, so that the microprogram is completed without a branch when the input source operand is a normalized number. On the other hand, when the input source operand is an unnormalized number, the microprocessor operates to branch to a normalizing program and to cause a normalized operand to be held in the temporary register and a code indicative of the temporary register to be set to the pointer. In addition, the microprocessor operates to re-execute the microprogram from the address designated by the address register.

Normalization control system for floating point arithmetic operation

A floating-point arithmetic processor performs a MASK or TRAP operation in response to occurrence of an exception. This processor includes a first flag which is set when the exception occurs, a second flag storing first data designating the MASK operation or second data designating the TRAP operation. A third flag is set when the first flag is set and the second flag is storing the second data. A controller produces a default value in response to the occurrence of the exception. The processor also includes a destination register, which is accessible by a central processing unit (CPU), and a transfer gate circuit which takes an open state to allow the default value to be stored into the destination register when the third flag is not set and a closed state to inhibit the default value to be stored into the destination register when the third flag is set.

Arithmetic processor performing mask and trap operations for exceptions

A microcomputer system includes a master processor and a coprocessor interconnected via a bus. The coprocessor supplies first, second and third signals to the master process, the first (BUSY) signal taking an active level when the coprocessor requests a wait condition of the master processor, the second (CPERR) signal taking an active level at least when the first signal is changed to the inactive level in a state of occurrence of an arithmetic exception in the coprocessor, and the third (CPEND) signal taking an active level when the coprocessor is free of execution of an instruction and of an occurrence of an arithmetic exception. When the coprocessor executes an instruction whose execution result is not required to be returned to the master processor, the master processor detects the level of the third signal and if the third signal is at the active level, the master processor starts to execute subsequent instructions irrespective of the first and second signals, in parallel with the execution of the instruction by the coprocessor.

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Tokyo, Japan

Shingo Kojima