Oki Electric Industry Co., Ltd.

Oki Semiconductor Co., Ltd.

Shingo Kazuma

Kenta Yamada

Atsuhiko Okada

Hideaki Wada

Mitsuaki Watanabe

Hirosuke Tabata

Hajime Iwai

An audio reproduction circuit has an input buffer for holding MP3 data. The audio reproduction circuit also has an MP3 decoder for reading and decoding, in certain processing units, the MP3 data held in the input buffer, and generating voice data. The audio reproduction circuit also has an output buffer for holding the voice data supplied from the MP3 decoder. The audio reproduction circuit also has a digital-analog converter for reading the voice data from the output buffer in synchronization with a clock signal, and converting the voice data to an audio signal. A cut-out detector is provided for generating a cut-out detection (prediction) signal on the basis of the quantity of MP3 data remaining in the input buffer and the quantity of voice data remaining in the output buffer. The cut-out signal indicates a timing at which MP3 data is to be introduced to the input buffer.

Audio reproduction circuit

An instruction code compression method and an instruction fetch circuit which are capable of reducing both the number of fetches and program codes. A reuse flag is provided in an upper bit group including operational codes, and a lower bit group including operands and having the same number of bits as the upper bit group. When 2N+1 (N is an integer of 1 or more) instruction codes having the same upper bit group continues in a series of instruction codes, respective reuse flags of the lower bit group of a 2n-th (n is an integer of 1 or more and N or less) instruction code and a (2n+1)-th instruction code in the series of instruction codes are set to '1', and the lower bit groups of the 2n-th and (2n+1)-th instruction codes are integreted into one compressed instruction code.

Instruction code compression using instruction codes with reuse flags

A circuit includes: a PLL circuit which multiplies a reference clock by a multiplication factor and outputs a PLL clock; a first counter which counts up with the PLL clock for a fixed period of time; a comparator which compares a count value of the first counter with the multiplication factor; a second counter which counts up the number of times the comparison values have been matched for the fixed period of time; and an output unit which generates an enable signal when a count value of the second counter reaches the number of times the circuit waits for stability, and opens a gate to transmit the PLL clock in response to the enable signal.

PLL output clock stabilization circuit

An interrupt signal EMG is put out to a microprocessorwhen a thermal monitordetects that a package temperature exceeds a reference. The microprocessor then increases a frequency division value N stored in a frequency division value registerof a clock mechanism. An inputted clock signal MCK is divided by N to generate a system clock signal SCK. Therefore, the frequency of system clock signal SCK decreases when N increases. Consequently, electricity consumption of each function modulei decreases and the package temperature is reduced.

Growing community of inventors

Tokyo, Japan

Shingo Kazuma