Semiconductor Technology Academic Research Center

Shingo Kagami

Masatoshi Ishikawa

Idaku Ishii

Takashi Komuro

A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.

Semiconductor integrated circuit device having a plurality of photo detectors and processing elements

A semiconductor integrated circuit device is provided which has a plurality of photo detector circuits and a plurality of processing elements. Each of the photo detector circuits includes a comparing circuit, which compares an output of a photo detector element with a reference voltage. A/D conversion is performed by counting the elapsed time until the output of the photo detector element drops below the reference voltage, and a level of the reference voltage as a function of time to be applied to the comparing circuit and time intervals of the counting are uniquely determined based on given quantization intervals of an amount of current generated by the photo detector element. In addition, the photo detector elements may be reset locally based on the result of the corresponding processing element.

Semiconductor integrated circuit device having photo detector circuits, processing elements, and comparing circuits which compare the output of a photo detector element with a reference voltage

Growing community of inventors

Tokyo, Japan

Shingo Kagami