Sumitomo Electric Device Innovations, Inc.

Sumitomo Electric Industries, Limited

Shingo Inoue

Ikuo Nakashima

Kaname Ebihara

A semiconductor device includes a metal base, a semiconductor chip provided on the metal base, and a frame work located on the metal base and having a metal pattern of an input pattern, an output pattern, and a bias pad. The bias pad and the input pattern or the output pattern are electrically connected by a conductor located on the frame work. The conductor has a characteristic of isolation at a frequency around an input signal or an output signal of the semiconductor device.

Semiconductor device

Disclosed is a package for a semiconductor device including a semiconductor die. The package includes a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess in its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.

Package for a semiconductor device

A semiconductor device package is disclosed. The package according to one example includes a base having a main surface made of a metal, a dielectric side wall having a bottom surface facing the main surface, a joining material containing silver (Ag) and joining the main surface of the base and the bottom surface of the side wall to each other, a lead made of a metal joined to an upper surface of the side wall on a side opposite to the bottom surface, and a conductive layer not containing silver (Ag). The conductive layer is provided between the bottom surface and the upper surface of the side wall at a position overlapping the lead when viewed from a normal direction of the main surface. The conductive layer is electrically connected to the joining material, extends along the bottom surface, and is exposed from a lateral surface of the side wall.

Semiconductor device package and semiconductor device

Disclosed is a semiconductor device including a semiconductor die, a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess on its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.

A process of assembling a semiconductor device is disclosed. The process includes steps of arraying metal bases on a carrier; applying sintered metal paste simultaneously onto the bases; disposing a substrate simultaneously onto the sintered metal paste where the substrate includes side walls corresponding to the bases and a wiring layer common the bases; and volatilizing solvent contained in the sintered metal paste.

Process of assembling semiconductor device

An RF amplifier with enhance power efficiency is disclosed. The RF amplifier traces the envelope of the input RF signal and varies the supply voltage to the final FET depending on the detected envelope through a linear power supply and a switching power supply superposed on the linear power supply. The linear power supply promptly responds the change of the envelope and gradually decreases the supply current as maintaining the supply voltage. The switching power supply takes over the supplement of the supply current to the final FET.

Amplifier having enhanced power efficiency

An RF amplifier that compensates the drift appearing after a sudden decrease of the drain current is disclosed. The RF amplifier detects the drain current by the bias control unit that feeds the change of the drain current back to the gate bias of the FET. The bias control unit responds to the sudden increase of the drain current by a relatively longer time constant; while, to the sudden decrease thereof by the second time constant enough shorter than the first time constant to compensate the drift appearing after the sudden decrease of the drain current.

Amplifier compensating drift after sudden decrease of drain current

An H-bridge driver without implementing with the PWM mode is disclosed. The H-bridge driver of the invention includes a non-inverting amplifier and an inverting amplifier commonly connected to the control signal. When the control signal exceeds the reference, the non-inverting amplifier commonly drives the first pair of transistors diagonally connected to the load. The low side transistor fully turns on but the high side transistor linearly operates. When the control signal is less than the reference, the inverting amplifier commonly drives the second pair of transistors also diagonally connected to the load.

Growing community of inventors

Yokohama, Japan

Shingo Inoue