Nec Corporation

Nec Electronics Corporation

Showa Aluminum Can Corporation

Shingo Hashimoto

Hitoshi Mitani

Noriyuki Ota

Hitoshi Tojima

Kenichi Minoshima

Masayuki Saitou

A plate attachment device and a method for attaching and removing printing plates, wherein the positioning accuracy in the circumferential direction relative to a plate cylinder is increased and attachment and removal of the printing plate is easy, are provided. The plate attachment deviceis equipped with a plate cylindersecured to the outer periphery of a plate drive shaftand having a cylindrical plate attaching surfaceto which a printing plateis to be attached from the tip end side of the plate drive shaft. The plate attaching surfaceis provided with a plurality of plate securing memberswhich are formed to be movable to both the outer side and inner side in the radial direction of the plate cylinder, abut the printing plateattached to the plate attaching surfaceand expand in the radial direction so as to adhere and secure the printing plateto the plate attaching surface

Plate attachment device and method for attaching/detaching printing plate

A pair of memory nodes, a capacitor of which one end is connected to the memory nodes, and a switch part which is connected to the other end of the capacitor, and changes a connection state of the other end of the capacitor when a semiconductor memory device operates at a speed not lower than a predetermined speed are included. By changing the connection state of the other end of the capacitor in accordance with the operation state of the semiconductor memory device like this, the influence which the capacitor connected to the memory node exerts on the operation speed of the semiconductor memory device can be suppressed.

Semiconductor memory device and method of operating the semiconductor memory device

A field-effect transistor has: a substrate having a first cavity; a gate electrode buried in the substrate; and diffusion layers formed in the substrate and being in contact with the first cavity. A channel region is formed substantially perpendicular to a surface of the substrate between the diffusion layers.

Field-effect transistor comprising hollow cavity

A semiconductor integrated circuit device is provided, which involves inhibiting a pattern change in the node interconnect and an increase of number of manufacturing process, when the capacitor is additionally installed in the SRAM, while providing higher reliability in the node interconnect. There is provided a semiconductor integrated circuit device, comprising: a node interconnect (lower capacitance electrode), being embedded in a trench formed in an interlayer insulating film provided on a semiconductor substrate, a surface of said lower capacitance electrode being formed to be substantially coplanar to a surface of the interlayer insulating film; and a capacitor, including: a capacitance insulating film, being flatly formed on a surface of the interlayer insulating film; and an upper capacitance electrode, being flatly formed thereon. Since the surface of the node interconnect is flat, forming thinner films of the capacitance insulating film and the upper capacitance electrode can be achieved, and the reliability of the capacitor is improved, and the planarization of the upper layer interconnects can be planarized to provide a miniaturization thereof.

Semiconductor integrated circuit device capacitive node interconnect

In a semiconductor device having a fusewhich makes connection between a first interconnectionand a second interconnection, and a first low heat-conductive sectionwhich makes connection between the first interconnectionand a third interconnectionat a site of the first interconnectionwhere the fuseis not connected, the first low heat-conductive sectionis fabricated from a material having a heat conductivity lower than that of the material to form the first interconnection. When the fuse is blown with the laser beam irradiation, the heat dissipation through the heat conduction along the fuse and the interconnection is to be suppressed, and thereby a satisfactory disconnection at the fuse is to be achieved.

Semiconductor device having a fuse and a low heat conductive section for blowout of fuse

The present invention discloses a semiconductor device, and a method of fabricating the same, where the semiconductor device has a gate electrode, a source-drain diffused layer of a first conductivity type, and a sidewall insulating film formed on the side face of the gate electrode, wherein the source-drain diffused layer has a lightly doped region formed below the sidewall insulating film, and a heavily doped region with impurity concentration higher than that of the lightly doped region, and the lightly doped region includes at least two kinds of impurities of the first conductivity type.

MOS transistor with double drain structure for suppressing short channel effect

A memory cell has a pair of n-ch drive MOS transistors, a pair of p-ch access MOS transistors. The access MOS transistor supply electric charge to storage nodes of the drive MOS transistors without using a resistive load. The gate insulation films of the drive MOS transistors have a thickness lower than the thickness of the gate insulation films of the access MOS transistors for achieving stable and high-speed operation of the memory cell.

Method of making loadless four-transistor memory cell with different gate insulation thicknesses for N-channel drive transistors and P-channel access transistors

Load-less four-transistor memory cell with different gate insulation thicknesses for N-channel drive transistors and P-channel access transistors

A semiconductor device includes a first conductivity type low concentration impurity layer provided around a thick silicon oxide film, which is formed for element isolation in a first conductivity type element region as a surface region in a semiconductor substrate, and a second conductivity type impurity layer which is provided immediately under at least the thick silicon oxide film. The second conductivity type impurity layer constitutes a channel stopper to enhance the effect of element isolation. The first conductivity type low concentration impurity layer has an effect of improving the P-N junction breakdown voltage of an active region in the first conductivity type element region, and suppresses the narrow channel effect of a MOS transistor in the first conductivity type element region.

Semiconductor device with impurity layer as channel stopper immediately

A static RAM has a low resistive contact film disposed in direct contact with a storage node of a memory cell and the gate electrode of a driver transistor in a through-hole, and in direct contact with an end portion of a high-resistance load. An accurate and stable resistance can be obtained for the high-resistance load without raising the contact resistance between the storage node and the gate electrode of the driver transistor.

Static RAM having a stable high-resistance load

The process of making a semiconductor device in which an n-channel MOSFET and a p-channel MOSFET are formed on the same semiconductor substrate is shortened. An impurity of p-type is ion-implanted vertically of a major surface of the semiconductor substrate to form p-type impurity doped layers in the embedding layers and p-type highly-concentrated impurity doped layers in the diffusion layers. Next, an impurity of n-type impurity is ion-implanted from obliquely above the semiconductor substrate major surface to form n-type highly-concentrated impurity doped layers in uppermost surfaces of the embedding layers. In the oblique ion-implantation, the n-type impurity is ion-implanted obliquely of the semiconductor substrate at a predetermined angle or more measured from a normal of the major surface of the semiconductor substrate so that semiconductor substrate portions (diffusion layers) at bottom ends of the contact holes for the p-channel MOSFET may not be viewed from obliquely above the semiconductor substrate major surface.

Growing community of inventors

Tokyo, Japan

Shingo Hashimoto