Nan Ya Technology Corporation

Micron Technology Incorporated

Inotera Memories, Inc.

Micro Technology, Inc.

Shing-Yih Shih

Tieh-Chiang Wu

Tse-Yao Huang

Neng-Tai Shih

Chiang-Lin Shih

Chih-Ching Lin

Hsu Chiang

Sheng-Fu Huang

Chien-Mao Liao

Yi-Nan Chen

Hsien-Wen Liu

Chang Rong Wu

Chang-Rong Wu

Jheng-Ting Jhong

Jeng-Ping Lin

Shih-Fan Kuan

Mao-Ying Wang

Hai-Han Hung

Jen-Jui Huang

Ya-Chih Wang

Wei-Cheng Shiu

Chih-Wei Cheng

Yu-Chi Sun

Tung-Wang Huang

Szu-Han Chen

Tzu En Ho

Hung-Mo Wu

Yu-Mei Ni

Cheng-Wei Wang

Tzu-Li Tseng

Hsin-Hung Ting

Ming-Tsung Ko

Shih-Yi Liu

Chien-Chang Cheng

A semiconductor structure includes a first chip and a second chip bonded to the first chip. The first chip includes a first semiconductor substrate, a first multi-level interconnect structure over the first semiconductor substrate, a first redistribution layer (RDL) over a conductive line of the first multi-level interconnect structure, a compact layer over the first RDL and the first multi-level interconnect structure, a cap layer over the compact layer, and a metal pad on the first RDL. The second chip includes a second semiconductor substrate, a second multi-level interconnect structure over the second semiconductor substrate, and conductive structure extending from the second multi-level interconnect structure to the metal pad.

Semiconductor structure

A method of manufacturing a semiconductor structure is provided. The method includes forming a thermal conductive structure embedded within a first passivation layer of a first wafer, and forming a plurality of conductive vias penetrating a first substrate of the first wafer and in contact with the thermal conductive structure. The method further includes forming a first connecting structure in contact with the thermal conductive structure and exposed by a surface of the first passivation layer. The method further includes bonding the first connecting structure of the first wafer to a second connecting structure of a second wafer, and bonding the first passivation layer of the first wafer to a first dielectric layer of the second wafer, wherein a first seal ring embedded within the first dielectric layer of the second wafer is thermally connected to the thermal conductive structure through the first connecting structure and the second connecting structure.

Method of manufacturing semiconductor structure having heat dissipation structure

A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.

Semiconductor device structure including a bonding structure

The present disclosure provides a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a first substrate, having a front side and a back side opposite to the front side; a first passivation layer over the front side of the first substrate; a second passivation layer over the back side of the first substrate, wherein the second passivation layer has a top surface facing away from the first substrate; a conductive feature disposed in the first passivation layer; a through substrate via penetrating through the second passivation layer and the first substrate; and a polymer liner between a sidewall of the through substrate via and the first substrate.

Semiconductor device with polymer liner and method for fabricating the same

The present application provides a semiconductor structure having vias with different dimensions and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; a second wafer including a second dielectric layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer; a passivation disposed over the second substrate; a first conductive via extending from the first conductive pad through the second wafer and the passivation, and having a first width surrounded by the second wafer; and a second conductive via extending from the second conductive pad through the passivation and the second substrate and partially through the second dielectric layer, and having a second width surrounded by the second wafer.

Semiconductor structure having vias with different dimensions

The present application provides a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die; a first redistribution structure positioned on the first die; a second die positioned on the first redistribution structure and comprising a first cache unit; and a third die positioned on the first redistribution structure, separated from the second die, and comprising a second cache unit. The first redistribution structure comprises: a plurality of conductive layers electrically coupled the first die and the first cache unit of the second die and electrically coupled the first die and the second cache unit of the third die, respectively and correspondingly; and a bridge layer electrically isolated from the plurality of conductive layers, electrically connected the second die and the third die. The first cache unit of the second die and the second cache unit of the third die are topographically aligned with the first die. The first die is configured as a cache memory, and the second die and the third die are configured as logic dies.

Semiconductor device with redistribution structure and method for fabricating the same

The present application provides a method of manufacturing a semiconductor structure having vias with different dimensions and a manufacturing method of the semiconductor structure. The method includes: providing a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; providing a second wafer including a second dielectric layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer; forming a passivation over the second substrate; forming a first conductive via extending from the first conductive pad through the second wafer and the passivation, and having a first width surrounded by the second wafer; and forming a second conductive via extending from the second conductive pad through the passivation and the second substrate and partially through the second dielectric layer, and having a second width surrounded by the second wafer.

Method of manufacturing semiconductor structure having vias with different dimensions

A semiconductor device includes a conductive pattern formed over a semiconductor substrate, and an interconnect structure formed over the conductive pattern. The semiconductor device also includes a first passivation layer over the conductive pattern; a second passivation layer over the first passivation layer; an interconnect structure disposed over the conductive pattern and in the first passivation layer and the second passivation layer; and an interconnect liner disposed between the interconnect structure and the conductive pattern and surrounding the interconnect structure, wherein inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern.

Method for preparing semiconductor device with composite passivation structure

A semiconductor structure is provided. The semiconductor structure includes a first substrate, a first dielectric layer disposed on the first substrate, a first passivation layer disposed on the first dielectric layer, a second substrate disposed on the first passivation layer, and a second substrate disposed on the first passivation layer. The semiconductor structure further includes a first seal ring embedded within the first dielectric layer and surrounds a circuit region of the first dielectric layer. The semiconductor structure further includes a thermal conductive structure embedded within the first passivation layer, wherein the thermal conductive structure is connected with the first seal ring through a first connecting structure.

Semiconductor structure having heat dissipation structure

The present application provides a semiconductor package structure having interconnections between dies, and a manufacturing method of the semiconductor package structure. The semiconductor package structure includes a first interposer including a first substrate and a first interconnect layer over the first substrate; a second interposer disposed over the first interposer, wherein the second interposer includes a second substrate and a second interconnect layer over the second substrate; a first die disposed over the first interposer and adjacent to the second interposer; a second die disposed over the second interposer; a first molding disposed over the second interposer and surrounding the second die; and a second molding disposed over the first interposer and surrounding the first die and the first molding, wherein the first interconnect layer includes a first communication member electrically connecting the first die to the second interposer and the second die.

Manufacturing method of semiconductor package structure having interconnections between dies

Semiconductor package structure having interconnections between dies and manufacturing method thereof

The present application provides a semiconductor structure having an elastic member within a via. The semiconductor structure includes a wafer including a substrate, a dielectric layer under the substrate, and a conductive pad surrounded by the dielectric layer; a passivation layer disposed over the substrate; a conductive via extending from the conductive pad through the substrate and the passivation layer and partially through the dielectric layer; and an elastic member disposed within the conductive via.

Semiconductor structure having elastic member within via

A semiconductor device includes a device layer with a semiconductor element, a first dielectric layer on the device layer, a first conductive line on the device layer and surrounded by the first dielectric layer, and a second dielectric layer on the first dielectric layer and around the first conductive line. The semiconductor includes a spacer disposed on the first conductive line and abutting a sidewall of the second dielectric layer, and a first conductive via disposed on the first conductive line and the spacer. The first conductive via includes a first segment positioned over the spacer and including a first width, and a second segment positioned between the first segment the first conductive line and including a second width. The first width is larger than the second width.

Semiconductor device

A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.

Semiconductor package structure and method for preparing the same

A method of manufacturing a semiconductor structure includes: providing a first wafer including a first substrate, a first dielectric layer under the first substrate, and a first conductive pad surrounded by the first dielectric layer; disposing a first passivation layer over the first substrate; removing portions of the first dielectric layer, the first substrate and the first passivation layer to form a first opening exposing a portion of the first conductive pad; disposing a first conductive material within the first opening; disposing a first elastic material within the first opening and surrounded by the first conductive material; removing portions of the first conductive material and the first elastic material adjacent to an end of the first opening to form a first elastic member; and disposing a second conductive material over the first elastic member and the first conductive material to form a first conductive via surrounding the first elastic member.

Growing community of inventors

Taipei, Taiwan

Shing-Yih Shih