Sun Microsystems, Inc.

Shing I Kong

Edmund Joseph Kelly

Robert Cmelik

Charles E Narad

Yousef A Khalidi

Madhusudhan Talluri

Michael L Powell

Stephen Alan Chessin

David Ditzel

Glen R Anderson

A method and apparatus for translating a virtual address to a physical address. A virtual address to be translated has a virtual page offset and a virtual page number. The virtual address to be translated addresses a page of memory. The size of this page is unknown. There are L different possible page sizes where L is a positive integer greater than one. Each of the L different page sizes is selected to be a test page size and a test is performed. During the test, a pointer into a translation storage buffer is calculated. The pointer is calculated from the virtual address to be translated by assuming that the virtual address to be translated corresponds to a mapping of the test page size. The pointer points to a candidate translation table entry of the translation storage buffer. The candidate translation table entry has a candidate tag and candidate data. The candidate tag identifies a particular virtual address and the candidate data identifies a particular physical address corresponding to the particular virtual address. A virtual address target tag is extracted from the virtual address to be translated. The virtual address target tag is calculated by assuming that the virtual address to be translated corresponds to a mapping of the test page size. The target tag and the candidate tag are then compared. If the target tag matches the candidate tag, the candidate data is provided as the physical address translation corresponding to the virtual address to be translated.

Virtual address to physical address translation of pages with unknown

A backward compatible addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers. The computer system of the present invention has a processor capable of manipulating numbers having precision S, where S is a power of 2. The memory locations are specified in an instruction address field by an n-bit logical address ##EQU1## Each S-precision number is stored in a group of S memory locations accessed by an m-bit physical address ##EQU2## Each memory location is capable of storing a single precision number. Addressing logic for addressing the memory locations with the logical addresses includes alignment logic for setting:

Memory addressing scheme for increasing the number of memory locations

Virtual address to physical address translation cache that supports

A memory management unit for translating a virtual address into a corresponding physical address including a translation lookaside buffer and a comparator. The translation lookaside buffer includes a plurality of entries, each of the entries having a first number of bits to indicate a virtual page number, a second number of bits to indicate an offset into the page, a third number of bits to indicate either a portion of a page number or a portion of an offset value, a fourth number of bits to indicate a page size, and a fifth number of bits for storing a physical address of a page of memory. The comparator compares a number of bits equal to the virtual page size of a virtual address presented to the translation lookaside buffer with the virtual addresses stored in entries of the translation lookaside buffer. If the result of the comparison produces a match/hit, the physical address is concatenated with the bits of the second and third number of bits using the stored page size to provide a physical address. When the comparison produces a miss, an assumed page size is used to access a table in memory from which the physical addresses may be derived.

Method and apparatus for a memory management unit supporting multiple

The present invention enables a computer system to store from register files to memory, and restore from memory back to the register files, data from programs designed to operate in accordance with a first word size, as well as programs designed to operate in accordance with a second word size. This is accomplished without an increase in hardware and without requiring modification of existing software. In particular, an indication is utilized at the procedure level to designate whether a particular procedure is using words of a first or second word size. Preferably, this indication is placed in a first predetermined bit position in the stack pointer of the procedure. When a save occurs, certain contents from the register file are saved to memory along with the stack pointer. Under certain circumstances, the word size indication is moved to a second predetermined bit position within the stack pointer which is stored in a predesignated stack pointer address in the save area. When the contents are restored from memory, back to the register file, the indication is reviewed in the stack pointer address and serves to determine the word size of the procedure being restored.

Extending computer architecture from 32-bits to 64-bits by using the

A method and apparatus are provided for enabling a computer that is capable of running programs utilizing different address sizes to run those programs without having to modify the computer's hardware. A mask register is used to identify bits of a sum of register addresses that are valid for the program that is running. The number of valid bits in the register mask can be changed to correspond to the addressable memory size for different programs.

Growing community of inventors

Menlo Park, CA, United States of America

Shing I Kong