Taiwan Semiconductor Manufacturing Comp. Ltd.

Shing-Huang Wu

Chia-Wei Liu

Jheng-Hong Jiang

Jian-Shian Chen

Chung-Nang Chen

A RRAM device is provided. The RRAM device includes: a bottom electrode in a first dielectric layer; a switching layer in a second dielectric layer over the first dielectric layer, wherein a conductive path is formed in the switching layer when a forming voltage is applied; and a tapered top electrode region in a third dielectric layer over the second dielectric layer, wherein the tapered top electrode region extends downwardly into the switching layer.

Resistive random access memory device

A semiconductor structure is provided. The semiconductor structure includes a substrate, a pillar structure, a fin structure, and a buffering structure. The pillar structure is disposed on the substrate. The fin structure is connected to the pillar structure and is separate from the substrate. The buffering structure is disposed in the fin structure and includes a soft material layer and an air gap surrounded by the soft material layer. A method of manufacturing the semiconductor structure is also provided.

Semiconductor structure and method of manufacturing the same

A micromechanical arm is provided. The micromechanical arm includes: a bottom metal piece having a plurality of trenches extending downwardly from a top surface of the bottom metal piece; an intermediate layer on the bottom metal piece and filling at least a portion of each of the plurality of trenches; and a top metal piece on the intermediate layer. The intermediate layer is made of a material that has a stiffness smaller than the bottom metal piece and the top metal piece.

Impact-resistant micromechanical arms

Devices and methods of manufacture for a graduated, 'step-like,' capacitance structure having two or more capacitors. A semiconductor structure comprising a capacitor structure, the capacitor structure comprising a first capacitor and a second capacitor. The first capacitor comprising a first bottom electrode and a top electrode having a bottom surface that is a first distance from a top surface of the first bottom electrode. The second capacitor comprising a second bottom electrode and the top electrode, in which the bottom surface is a second distance from a top surface of the second bottom electrode, and in which the first distance is different from the second distance.

Variable graduated capacitor structure and methods for forming the same

A damping device is provided. The damping device includes a damper including a mechanical deflector. The damping device includes a post coupled to the mechanical deflector. The damping device includes a case in which the damper is disposed.

Damping device and method of making

Devices and methods of manufacture for a graduated, 'step-like,' semiconductor structure having two or more resonator trenches. A semiconductor structure may comprise a first resonator and a second resonator. The first resonator comprising a first metallic resonance layer and a capping plate having a bottom surface that is a first distance from a distal end of the first metallic resonance layer. The second resonator comprising a second metallic resonance layer and the capping plate, in which the bottom surface is a second distance from a from a distal end of the second metallic resonance layer, and in which first distance is different from the second distance.

Cavity resonator for enhancing radio-frequency performance and methods for forming the same

A RRAM device is provided. The RRAM device includes: a bottom electrode in a first dielectric layer; a switching layer in a second dielectric layer over the first dielectric layer, wherein a conductive path is formed in the switching layer when a forming voltage is applied; and a needle-like-shaped top electrode region in a third dielectric layer over the second dielectric layer. The needle-like-shaped top electrode region includes: an oxygen-rich dielectric layer, wherein a lower end of the oxygen-rich dielectric layer is a tip; and a top electrode over the oxygen-rich dielectric layer.

Resistive random access memory device having needle-like-shaped top electrode region and method for fabricating the same

A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.

Plasma-damage-resistant interconnect structure and methods for forming the same

A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.

Pit-less chemical mechanical planarization process and device structures made therefrom

A method of forming a semiconductor structure includes forming a first conductive contact in a first dielectric layer coupled to a first device and forming a second conductive contact in the first dielectric layer coupled to a second device. A first trench is formed in the first dielectric layer having a first depth and exposing at least a portion of the first conductive contact. A second trench is formed in the first dielectric layer having a second depth different than the first depth and exposing at least a portion of the second conductive contact. A first conductive layer is formed in the first trench and the second trench. A second dielectric layer is formed in the first trench and the second trench over the first conductive layer.

Semiconductor structure and method of making

A near eye display system is provided. The near eye display system includes: a frame comprising a main body and two temple arms; at least one near eye sensor mounted on the main body and configured to measure user eye parameters; a first near eye display mounted on the main body and configured to form a first image projected on a first retina of a first eye; a second near eye display mounted on the main body and configured to form a second image projected on a second retina of a second eye; and a processing unit located at least at one of the two temple arms and configured to generate a display control signal based at least on the user eye parameters, wherein the display control signal drives the first near eye display and the second near eye display.

Near eye display apparatus

A near-eye display includes a semiconductor substrate that has a first curved surface and a second curved surface opposite to each other, and a plurality of luminous pixels formed over the first curved surface of the semiconductor substrate. The luminous pixels cooperatively form a display area of the near-eye display. The second curved surface of the semiconductor substrate is formed with a plurality of indentations at a portion that corresponds in position to the display area.

Display device having display area with luminous pixels over curved surface of semiconductor substrate for use in near-eye display

A MEMS package and a method for forming a MEMS package are provided. The MEMS package includes a package substrate, a housing structure, an image sensor structure, a MEMS structure and a composite damper. The housing structure includes a stopper. The image sensor structure and the MEMS structure are between the package substrate and the housing structure. An interconnect wire electrically connects the MEMS structure to the image sensor structure. The composite damper is between the package substrate and the housing structure. The composite damper is configured to control a gap between the interconnect wire and the stopper.

Growing community of inventors

Hsin-Chu, Taiwan

Shing-Huang Wu