International Business Machines Corporation

Shing Chou Pi

Gerald Bernard Long

Donald W Price

Richard Charles Paddock

Ralph C Mitchell

Arthur Wilbert Holmes, Jr

This specification describes arrays for performing logic functions. In these arrays input variables are placed on a series of parallel input lines that intersect a number of parallel output lines in a grid of intersections. Field effect devices at these intersections have their gate terminals connected to one of the input lines and their source terminal connected to one of the output lines and through a load device to a source of potential. The drain terminals of these devices are either unconnected, connected directly to ground or connected to ground through one of two switching devices. The devices with unconnected drains are inoperative. The devices with their drains connected directly to ground are operative at all times. While the devices connected to ground through one of the switches are operative only when the switch is closed. The array can be time shared by two different logic functions by having one or the other of the switches off at any given time.

Time shared programmable logic array

A self-sequenced read only memory is shown wherein each word line contains dynamic logic circuits for energizing a next word line after the fixed time delay provided by the dynamic logic circuits. Self-sequencing inverters are physically placed within the array area thereby increasing reliability and reducing circuit wiring. When used as a microprogram control storage, the memory is divided into a plurality of self-sequenced control routines. When a certain function is to be performed, the first word line of the control routine for performing the selected function is energized. Since each word line includes a one cycle delay and is wired to the next sequential word line, no separate timing or address control is required to address word lines within a selected control routine. Once a control routine is energized, sequential microinstructions will be automatically fetched including branch and branch-on condition instructions. Branch operations can be implemented by connecting one of the outputs of the array to the branched-to word line. Branch-on condition can be implemented by gating the inverter in the branched-to instruction with an AND circuit. By virtue of the self-sequencing of the memory, branched-to word lines can be sequentially accessing memory words simultaneously with sequential memory word fetch operations within the branched from control routine. The branched-to control routine thereby acts as a modifier routine to modify the bit patterns of the memory words which continue to be fetched by the branched-from control routine.

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Shing Chou Pi