Western Digital Technologies, Inc.

Sandisk Information Technology (shanghai) Co., Ltd.

Shineng Ma

Chin-Tien Chiu

Yazhou Zhang

Chih-Chin Liao

Xuyi Yang

Ye Bai

Hem P Takiar

Lei Shi

Cong Zhang

Ting Liu

Hope Chiu

Yangming Liu

Binbin Zheng

Yanwen Bai

JinXiang Huang

Kent Yang

A semiconductor device package includes a substrate, a first heat-generating component positioned on a surface of the substrate, an encapsulant at least partially encapsulating the first heat-generating component, and one or more channels extending through a portion of the encapsulant toward the first heat-generating component. Each of the one or more channels contains a thermally conductive material having a thermal conductivity greater than a thermal conductivity of the encapsulant.

Semiconductor device package having thermally conductive pathways

A memory card includes a memory card body dimensioned to house at least one integrated circuit die package. The memory card body, in certain embodiments, includes a first surface spaced apart from a second surface and a plurality of side surfaces connecting the first surface to the second surface. The memory card also includes a contact pad disposed on at least one side surface of the plurality of side surfaces. The contact pad includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer.

Side contact pads for high-speed memory card

A semiconductor die is provided. The semiconductor die includes: at least one complementary metal oxide semiconductor (CMOS) circuit module electrically coupled to at least one memory die, the at least one memory die being separated from the semiconductor die; and a controller module electrically coupled to the CMOS circuit module and configured to control the at least one CMOS circuit module and the at least one memory die. A semiconductor package is also provided.

Semiconductor die and semiconductor package

A semiconductor device is disclosed including wafers of stacked integrated memory modules. A semiconductor device of the present technology may include multiple memory array semiconductor wafers, and a CMOS controller wafer, which together, operate as a single, integrated flash memory semiconductor device. In embodiments, the CMOS controller wafer may include semiconductor dies comprising ASIC logic circuits integrated together with memory array logic circuits.

High capacity semiconductor device including bifurcated memory module

A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.

Semiconductor device including control switches to reduce pin capacitance

A semiconductor device is disclosed including a stack of wafers having a densely configured 3D array of memory die. The memory die on each wafer may be arranged in clusters, with each cluster including an optical module providing an optical interconnection for the transfer of data to and from each cluster.

Semiconductor device including optically connected wafer stack

Growing community of inventors

Shanghai, China

Shineng Ma