Tokyo Electron Limited

Shin Uchida

Tetsuya Kagami

Hiroshi Yamada

Jun Fujihara

Tomoya Endo

Kentaro Konishi

Takanori Hyakudomi

Hiroaki Hayashi

Kenichi Narikawa

Xingjun Jiang

Hiroki Shikagawa

Katsuaki Sugiyama

Yukinori Murata

Rika Ozawa

A testing system includes: an inspection module including a plurality of levels of inspection chambers in each of which a tester part having a tester configured to perform an electrical inspection of an inspection object and a probe card is accommodated; an aligner module configured to align the inspection object with the tester part; an alignment area in which the aligner module is accommodated; and a loader part configured to load the inspection object into the alignment area and unload the inspection object out of the aligner module, wherein the inspection module is located adjacent to the alignment area.

Testing system

An analysis device analyzes inspection results of an inspection object which includes inspection target devices having respective electrodes on which needle marks are formed. The analysis device includes a display part for displaying an image, and an image generation part for generating an image to be displayed on the display part. The image generation part generates an analysis image based on information on inspection results with respect to the needle marks. The analysis image includes a needle mark scatter plot image showing positions of the needle marks with respect to the electrodes in each inspection target device in an overlapped manner, an inspection object map image showing a surface of the inspection object and showing needle mark inspection results with respect to the inspection target devices, and a captured image of the electrodes. Display contents of the images are linked with each other.

Analysis device and image generation method

An inspection system is provided with a prober and a tester. The tester includes a plurality of tester module boards on which a plurality of LSIs respectively corresponding to a plurality of devices under test (DUT) are mounted; a display unit which displays a wafer map indicating inspection results of the plurality of DUTs and/or self-diagnosis results of the tester; and a tester control unit which includes a wafer map drawing application for drawing the wafer map displayed on the display unit. The wafer map drawing application causes the inspection results and/or the self-diagnosis results to be displayed for each of the plurality of DUTs in a stepwise manner. In the wafer map, the plurality of DUTs are respectively linked to correspond to the plurality of LSIs mounted on the plurality of tester module boards.

Inspection system, wafer map display, wafer map display method, and computer program

Growing community of inventors

Nirasaki, Japan

Shin Uchida