Macronix International Co., Ltd.

Shin Su

Tao-Cheng Lu

Chun-Hsiang Lai

Meng-Huang Liu

Yen-Hung Yeh

Chia-Ling Lu

Chen-Shang Lai

Cheng-Chi Lin

Shih-Chin Lien

Chien-Wen Chu

Chin-Pen Yeh

Cha-Ling Lu

The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.

Laterally double-diffused metal oxide semiconductor transistor and method for fabricating the same

In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad

An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.

Electrostatic protection circuit

A device for connection between supply buses in mixed power integrated circuits includes a diode in series with a transistor with an active p-ring in a semiconductor substrate. The active p-ring surrounds the source and drain of the transistor with a conductive region having the same conductivity type as the semiconductor substrate. A control circuit coupled to the p-ring applies a bias voltage in response to an ESD event affecting the first and second conductors. The bias voltage tends to inject carriers into the semiconductor substrate which enables discharge of the short voltage pulse via a parasitic SCR in the substrate from the anode of the diode to the source of the transistor.

Electrostatic discharge conduction device and mixed power integrated circuits using same

An electro-static discharge (ESD) protection circuit for a dual polarity I/O pad is provided. The protection circuit includes a substrate of first type; a deep well region of second type disposed in the first type substrate; a well region of first type disposed in the second type deep well region; a first transistor disposed over the well region of first type, wherein the first transistor has a first source, a first gate and a first drain; a second transistor disposed over the substrate of first type, wherein the second transistor has a second source, a second gate and a second drain, and the second source is connected with the first drain, and both of them are disposed in a portion of the well region of first type, the deep well region of second type and the substrate of first type; a first doped region is disposed in the first type well region and laterally adjacent to the first source; a second doped region is disposed in the substrate of first type and laterally adjacent to the second drain.

Electro-static discharge protection circuit for dual-polarity input/output pad

An ESD protection apparatus for a high-voltage input pad comprises a modulator connected between the input pad and a snapback device with first and second guard rings surrounding the modulator, third guard ring surrounding the snapback device, and first and second guard ring control circuits to control the guard rings such that the protection apparatus has higher triggering and holding voltages under normal operation and lower triggering and holding voltages under ESD event.

ESD protection apparatus and method for a high-voltage input pad

The present invention relates an electrostatic discharge (ESD) protection device that is applied to a mixed voltage circuit assembly. The device comprises a RC controlled circuit subassembly and a field transistor, which the RC controlled circuit is coupled with the mixed voltage circuit assembly to substantially control the ESD protection device to be ON or OFF. The field transistor is coupled between a first power supply and a second power supply of said mixed voltage circuit assembly, which is off on the condition of a normal operating condition and is conducting as an ESD event occurred.

RC controlled ESD circuits for mixed-voltage interface

An ESD protection apparatus for dual-polarity input pad comprises a triple-well formed with a first, second and third regions to form an SCR structure. A first and second ground connection regions of opposite conductivity types are formed on the first region, a first and second input connection regions of opposite conductivity types are formed in the third region, and a bridge region is formed across the second region and extends to the first and third regions. Under normal operation, the first, second, and third regions form two back-to-back diodes. Under positive polarity ESD event, breakdown is occurred between the bridge and first regions to thereby trigger an SCR circuit for positive polarity ESD protection. Under negative polarity ESD event, breakdown is occurred between the bridge and third regions to thereby trigger an SCR circuit for negative polarity ESD protection.

ESD protection apparatus and method for dual-polarity input pad

The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.

Silicon controlled rectifier structure with guard ring controlled circuit

A gate-equivalent-potential circuit and method for an I/O pad ESD protection arrangement including used and unused MOS fingers connected to the I/O pad comprises a switch connected between the gates of the MOS fingers, an ESD detector connected to the switch to turn on the switch upon an ESD event and a gate-modulated circuit connected to the gate of the unused finger to couple a voltage thereto to reduce the triggering voltage of the transistors within the fingers.

Gate-equivalent-potential circuit and method for I/O ESD protection

An electrostatic discharge (ESD) device used with a high-voltage input pad is described. The ESD device serves as a secondary device of a two-stage protection circuit, and comprises a substrate, a first MOS transistor and a second MOS transistor. The first MOS transistor is disposed on the substrate and comprises a first gate, a first drain and a first source, wherein the first gate is coupled to a bias Vg , and the first drain is coupled to the high-voltage input pad. The second MOS transistor is disposed on the substrate and comprises a second gate, a second drain and a second source, wherein the second gate and the second source are both grounded, and the second drain is electrically connected with the first source of the first MOS transistor.

ESD device used with high-voltage input pad

A substrate pump circuit and method for I/O ESD protection including NMOS fingers connected to the interconnection between an I/O pad and an internal circuit comprises a MOS device connected to the interconnection between the I/O pad and the internal circuit and the substrate under the control of a switch to turn it on to conduct a pumping current through the substrate resistor when the I/O pad is under ESD stress, so as to pull up the potential of the substrate adjacent to the NMOS fingers, resulting in the reduction of the triggering voltage of the NMOS fingers.

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Hsinchu, Taiwan

Shin Su