Hitachi Maxell, Limited

Sharp Kabushiki Kaisha Corporation

Shin Shimizu

Satoshi Kawamura

Katsuji Iguchi

Seizo Kakimoto

Tsukasa Doi

Fumiyuki Inose

Toshiyuki Kaneko

An information carrier in which an IC element formed integrally with a coil is mounted and which has an extended communication range and a method of manufacturing the same and a structure of the IC element appropriately suited for this sort of information carrier and a method of manufacturing the same. In the IC element, a conductor constituting the coilis implemented in a multilayer structure including a metal-sputtered layer or alternatively a metal-evaporated layerand a metal-plated layer. In the method of manufacturing the IC element, a precision electroforming method is employed as a means for forming the metal-plated layer. The information carrier is implemented in such a structure in which the IC elementis disposed at a center portion in a planar direction of a substrate. In a method of manufacturing the information carrier, strip material or materialstoa given one of which has mounted thereon desired parts inclusive of the IC elements are manufactured, whereon desired information carriersare formed by punching the strip material(s).

Method of manufacturing an IC coil mounted in an information carrier

An information input/output unit according to the present invention includes a receiving cavity capable of accommodating therein two different species of noncontact information media having shapes differing from each other and an antenna part capable of performing communication by radio with the noncontact information media. The unit can communicate with a close-fit-type noncontact information medium without fail and preferably with predetermined degree of freedom for the shapes of the media.

Information input/ output unit

A semiconductor memory device is provided which includes a plurality of memory cells, each of which includes: an active region having an MOS transistor formed in the surface portion of a semiconductor substrate; a gate electrode formed on the substrate for the MOS transistor so as to divide the active region into a source-side active region with a storage contact and a drain-side active region with a bit contact, the portion of the active region which is positioned under the gate electrode functioning as a channel region for the MOS transistor; a first impurity-implanted region formed in a portion of the source-side active region so as to overlap with part of the storage contact and the gate electrode, the portion of the source-side active region which overlaps with the first impurity-implanted region functioning as a source region for the MOS transistor; and a second impurity-implanted region formed in a portion of the drain-side active region so as to overlap with at least one part of the bit contact and the gate electrode, the portion of the drain-side active region which overlaps with the second impurity-implanted region functioning as a drain region for the MOS transistor.

Semiconductor memory device

Growing community of inventors

Kawasaki, Japan

Shin Shimizu