Taiwan Semiconductor Manufacturing Comp. Ltd.

Applied Materials, Inc.

Taiwan Semiconducotr Manufacturing Company, Ltd.

Shin-Puu Jeng

Po-Yao Lin

Chen-Hua Douglas Yu

Shu-Shen Yeh

Shang-Yun Hou

Feng-Cheng Hsu

Chin-Hua Wang

Shuo-Mao Chen

Ming-Chih Yew

Po-Yao Chuang

Hsien-Wei Chen

Po-Hao Tsai

Wen-Chih Chiou

Chia-Kuei Hsu

Yu-Sheng Lin

Jing-Cheng Lin

Po-Chen Lai

Techi Wong

Hao-Yi Tsai

Wei-Cheng Wu

Jui-Pin Hung

Der-Chyang Yeh

Hsien-Pin Hu

Hsien-Wen Liu

Kim Hong Chen

Wensen Hung

Cheng-Chieh Hsieh

Wai-Fan Yau

David Wingto Cheung

Yi-Wen Wu

Cheng-Lin Huang

Kuo-Ching Hsu

Szu Wei Lu

Chi-Hsi Wu

Tzuan-Horng Liu

Yung-Cheng Lu

Ying-Ching Shih

An-Jhih Su

Farhad K Moghadam

Michael S Barnes

Tetsuya Ishikawa

Robert Parkash Mandal

Jie Chen

Sao-Ling Chiu

Szu-Wei Lu

Ying-Ju Chen

Hsueh-Chung Chen

Hsiao-Wen Lee

Chia-Lun Tsai

Tsang-Jiuh Wu

Ming-Yen Chiu

Li-Hsien Huang

Weng-Jin Wu

Ku-Feng Yang

Chih-Hsien Lin

Hsiao-Tsung Yen

Chih-Wei Wu

Cheng-Hsien Hsieh

Li-Qun Xia

Ellie Y Yieh

Ching-Wen Hsiao

Chien-Hung Chen

Chih-Hang Tung

Mill-Jer Wang

Bruce C S Chou

Yi-Li Hsiao

Chung-Shi Liu

Mirng-Ji Lii

Chao-Wen Shih

Chi-I Lang

Pei-Haw Tsao

Chin-Fu Kao

Hsin-Hui Lee

Li-Han Hsu

Chin-Chuan Chang

Chen-Shien Chen

Hung-Jui Kuo

Chenming Hu

Chih-Hua Chen

Chen-Cheng Kuo

Chien-Hung Zordius Chen

Hsin-Yu Chen

Ming Hung Tseng

Tsung-Yu Chen

Jyh-Cherng Sheu

Chun-Jen Chen

Ming-Fa Chen

Carlos H Diaz

Srinivas D Nemani

Kong-Beng Thei

Shankar Venkataraman

Tsung-Shu Lin

Chun-Hung Chen

Chine-Gie Lou

Chin-Yu Ku

Harry Hak-Lay Chuang

Yi-Ming Sheu

Hsi-Kuei Cheng

Sheng-Chen Chung

Chien-Hsiun Lee

A package structure is provided. The package structure includes a redistribution structure and a semiconductor chip over the redistribution structure. The package structure also includes an adhesive element over the semiconductor chip. Opposite outermost edges of the adhesive element are laterally between opposite outermost edges of the redistribution structure. The package structure further includes a protective layer laterally surrounding the semiconductor chip and the adhesive element. In addition, the package structure includes a thermal conductive element over the semiconductor chip. The thermal conductive element is surrounded by the adhesive element.

Package structure with adhesive element over semiconductor chip

Some implementations described herein provide a semiconductor package including an integrated circuit die mounted to an interposer using connection structures. An underfill material between the integrated circuit die and the interposer includes shaped fillets that are below a plane corresponding to a bottom surface of the integrated circuit die. The underfill material including the shaped fillets reduces a likelihood of stresses and/or strains that damage a mold compound from transferring to the mold compound from the underfill material, the integrated circuit die, and/or the interposer. In this way, a quality and reliability of the semiconductor package including the underfill material with the shaped fillets is reduced. By improving the quality and reliability of the semiconductor package, a yield of the semiconductor package may increase to decrease a cost of the semiconductor package.

Semiconductor package and method of manufacturing

A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.

Semiconductor package and method of manufacturing the same

Devices and method for forming a chip package structure including a package substrate, a fan-out package attached to the package substrate, a first adhesive layer attached to a top surface of the package substrate, a beveled stiffener structure attached to the package substrate and surrounding the fan-out package, the beveled stiffener structure comprising at least one tapered sidewall, in which a first width of a top portion of the beveled stiffener structure along the at least one tapered sidewall is greater than a second width of a bottom portion of the beveled stiffener structure along the at least one tapered sidewall, and in which the bottom portion is in contact with a top surface of the first adhesive layer.

Stiffener structure with beveled sidewall for footprint reduction and methods for forming the same

A package includes a package substrate, the package substrate having a first side and a second side opposite to the first side, a package component bonded to the first side of the package substrate, a front-side warpage control structure attached to the first side of the package substrate, and a backside warpage control structure embedded in the package substrate from the second side of the package substrate. The front-side warpage control structure includes a first disconnected structure and a second disconnected structure laterally separated from each other by a gap. The backside warpage control structure includes a third disconnected structure and a fourth disconnected structure laterally separated from each other.

Integrated circuit package and method of forming same

A semiconductor device and manufacturing process are provided wherein a first semiconductor device is electrically connected to redistribution structures. An antenna structure is located on an opposite side of the first semiconductor device from the redistribution structures, and electrical connections separate from the first semiconductor device connect the antenna structure to the redistribution structures.

Semiconductor device and method of manufacture

A method includes joining a first wafer to a second wafer, forming a first through-via penetrating through the first wafer and further extending into the second wafer, and forming a redistribution line on the first wafer. The redistribution line and the first through-via electrically connect a first conductive feature in the first wafer to a second conductive feature in the second wafer. An electrical connector is formed over the first wafer.

3D stacking architecture through TSV and methods forming same

A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.

Package structure

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

Semiconductor package including a semiconductor die disposed in a cavity and method for manufacturing thereof

A semiconductor structure includes a fan-out package comprising at least one semiconductor die, a redistribution structure including fan-out bonding pads, and a first underfill material portion located between the at least one semiconductor die and the redistribution structure; a packaging substrate comprising chip-side bonding pads; an array of solder material portions bonded to the chip-side bonding pads and the fan-out bonding pads; a second underfill material portion laterally surrounding the array of solder material portions; and at least one buffer block structure located between a respective neighboring pair of solder material portions within the array of solder material portions and between the fan-out package and the packaging substrate, and laterally surrounded by the second underfill material portion.

Buffer block structures for C4 bonding and methods of using the same

A bonded assembly including a first structure and a second structure is provided. The first structure includes first metallic connection structures surrounded of which a passivation dielectric layer includes openings therein, and first metallic bump structures having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane including a distal horizontal surface of the passivation dielectric layer. The second structure includes second metallic bump structures having a respective second horizontal bonding surface segment that protrudes toward the first structure. The first metallic bump structures is bonded to the second metallic bump structures through solder material portions.

Bridging-resistant microbump structures and methods of forming the same

A structure includes a first package component including a first conductive pad, and a second package component overlying the first package component. The second package component includes a surface dielectric layer, and a conductive bump protruding lower than the surface dielectric layer. The first conductive bump includes a first sidewall facing away from a center of the first package component, and a second sidewall facing toward the center. A solder bump joins the first conductive pad to the first conductive bump. The solder bump contacts the first sidewall. An underfill is between the first package component and the second package component, and the underfill contacts the second sidewall.

Bump joint structure with distortion and method forming same

A semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, where the package includes: an interposer, where a first side of the interposer is bonded to the first surface of the substrate through first conductive bumps; dies attached to a second side of the interposer opposing the first side; and a molding material on the second side of the interposer around the dies; a plurality of thermal interface material (TIM) films on a first surface of the package distal from the substrate, where each of the TIM films is disposed directly over at least one respective die of the dies; and a heat-dissipation lid attached to the first surface of the substrate, where the package and the plurality of TIM films are disposed in an enclosed space between the heat-dissipation lid and the substrate, where the heat-dissipation lid contacts the plurality of TIM films.

High efficiency heat dissipation using discrete thermal interface material films

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes an interposer substrate over the wiring substrate. The interposer substrate includes a redistribution structure, a dielectric layer, a conductive via, and a plurality of first dummy vias, the dielectric layer is over the redistribution structure, the conductive via and the first dummy vias pass through the dielectric layer, the first dummy vias surround the conductive via, and the first dummy vias are electrically insulated from the wiring substrate. The chip package structure includes a chip structure over the interposer substrate. The chip structure is electrically connected to the conductive via, and the chip structure is electrically insulated from the first dummy vias.

Method for forming chip package structure

A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

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Hsinchu, Taiwan

Shin-Puu Jeng