Taiwan Semiconductor Manufacturing Comp. Ltd.

Applied Materials, Inc.

Shin-Puu Jeng

Po-Yao Lin

Chen-Hua Douglas Yu

Shu-Shen Yeh

Shang-Yun Hou

Feng-Cheng Hsu

Chin-Hua Wang

Shuo-Mao Chen

Ming-Chih Yew

Po-Yao Chuang

Hsien-Wei Chen

Po-Hao Tsai

Wen-Chih Chiou

Chia-Kuei Hsu

Yu-Sheng Lin

Jing-Cheng Lin

Po-Chen Lai

Techi Wong

Hao-Yi Tsai

Wei-Cheng Wu

Meng-Liang Lin

Jui-Pin Hung

Der-Chyang Yeh

Hsien-Pin Hu

Hsien-Wen Liu

Kim Hong Chen

Wensen Hung

Cheng-Chieh Hsieh

Yi-Wen Wu

Wai-Fan Yau

David Wingto Cheung

Cheng-Lin Huang

Kuo-Ching Hsu

Szu Wei Lu

Chi-Hsi Wu

Tzuan-Horng Liu

Yung-Cheng Lu

Ying-Ching Shih

An-Jhih Su

Farhad K Moghadam

Michael S Barnes

Tetsuya Ishikawa

Robert Parkash Mandal

Jie Chen

Szu-Wei Lu

Ying-Ju Chen

Hsueh-Chung Chen

Hsiao-Wen Lee

Chia-Lun Tsai

Tsang-Jiuh Wu

Ming-Yen Chiu

Li-Hsien Huang

Weng-Jin Wu

Ku-Feng Yang

Chih-Hsien Lin

Hsiao-Tsung Yen

Chih-Wei Wu

Cheng-Hsien Hsieh

Li-Qun Xia

Ellie Y Yieh

Ching-Wen Hsiao

Chien-Hung Chen

Chih-Hang Tung

Mill-Jer Wang

Bruce C S Chou

Yi-Li Hsiao

Chung-Shi Liu

Mirng-Ji Lii

Chao-Wen Shih

Chi-I Lang

Pei-Haw Tsao

Chin-Fu Kao

Hsin-Hui Lee

Li-Han Hsu

Chin-Chuan Chang

Chen-Shien Chen

Hung-Jui Kuo

Chenming Hu

Chih-Hua Chen

Chen-Cheng Kuo

Chien-Hung Zordius Chen

Hsin-Yu Chen

Ming Hung Tseng

Tsung-Yu Chen

Jyh-Cherng Sheu

Chun-Jen Chen

Ming-Fa Chen

Carlos H Diaz

Srinivas D Nemani

Kong-Beng Thei

Shankar Venkataraman

Tsung-Shu Lin

Chun-Hung Chen

Chine-Gie Lou

Chin-Yu Ku

Harry Hak-Lay Chuang

Yi-Ming Sheu

Hsi-Kuei Cheng

Jian-Hong Lin

Chien-Hsiun Lee

A method of fabricating integrated passive device dies includes forming a first plurality of integrated passive devices on a substrate, forming a plurality of micro-bumps on the first plurality of integrated passive devices such that the plurality of micro-bumps act as electrical connections to the integrated passive devices, and dicing the substrate to form an integrated passive device die including a second plurality of integrated passive devices. The micro-bumps may be formed in an array or staggered configuration and may have a pitch that is in a range from 20 microns to 100 microns. The integrated passive devices may each include a seal ring and the integrated passive device die may have an area that is a multiple of an integrated passive device area. The method may further include dicing the substrate in various ways to generate integrated passive device dies having different sizes and numbers of integrated passive devices.

Integrated passive device dies and methods of forming and placement of the same

A package assembly includes a package substrate including a molding material layer and a plurality of substrate portions embedded in the molding material layer, a redistribution layer (RDL) structure on the package substrate, and a plurality of semiconductor devices on the RDL structure.

Reconstructed substrates for high I/O counts application and methods for forming the same

A semiconductor device includes: a die having die connectors at a front side of the die; a molding material around the die; and a redistribution structure, where the die connectors of the die are attached to a first side of the redistribution structure, where the redistribution structure includes: a dielectric layer; a conductive line extending along a first surface of the dielectric layer facing the die; and a warpage tuning layer contacting and extending along a first surface of the conductive line facing the die, where a first coefficient of thermal expansion (CTE) of the conductive line is smaller than a second CTE of the warpage tuning layer.

Redistribution structure with warpage tuning layer

Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.

Semiconductor device and method of manufacture

Devices and method for forming a chip package structure including at least one semiconductor die attached to a redistribution structure, a molding compound die frame laterally surrounding the at least one semiconductor die, and a first underfill material portion located between the redistribution structure and the at least one semiconductor die and contacting sidewalls of the at least one semiconductor die and sidewalls of the molding compound die frame. The first underfill material portion may include at least one cut region, in which the first underfill material portion may include a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.

Chip package structure including an underfill material portion comprising a cut region

A package structure is provided. The package structure includes a redistribution structure and a semiconductor chip over the redistribution structure. The package structure also includes an adhesive element over the semiconductor chip. Opposite outermost edges of the adhesive element are laterally between opposite outermost edges of the redistribution structure. The package structure further includes a protective layer laterally surrounding the semiconductor chip and the adhesive element. In addition, the package structure includes a thermal conductive element over the semiconductor chip. The thermal conductive element is surrounded by the adhesive element.

Package structure with adhesive element over semiconductor chip

Some implementations described herein provide a semiconductor package including an integrated circuit die mounted to an interposer using connection structures. An underfill material between the integrated circuit die and the interposer includes shaped fillets that are below a plane corresponding to a bottom surface of the integrated circuit die. The underfill material including the shaped fillets reduces a likelihood of stresses and/or strains that damage a mold compound from transferring to the mold compound from the underfill material, the integrated circuit die, and/or the interposer. In this way, a quality and reliability of the semiconductor package including the underfill material with the shaped fillets is reduced. By improving the quality and reliability of the semiconductor package, a yield of the semiconductor package may increase to decrease a cost of the semiconductor package.

Semiconductor package and method of manufacturing

A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.

Semiconductor package and method of manufacturing the same

Devices and method for forming a chip package structure including a package substrate, a fan-out package attached to the package substrate, a first adhesive layer attached to a top surface of the package substrate, a beveled stiffener structure attached to the package substrate and surrounding the fan-out package, the beveled stiffener structure comprising at least one tapered sidewall, in which a first width of a top portion of the beveled stiffener structure along the at least one tapered sidewall is greater than a second width of a bottom portion of the beveled stiffener structure along the at least one tapered sidewall, and in which the bottom portion is in contact with a top surface of the first adhesive layer.

Stiffener structure with beveled sidewall for footprint reduction and methods for forming the same

A package includes a package substrate, the package substrate having a first side and a second side opposite to the first side, a package component bonded to the first side of the package substrate, a front-side warpage control structure attached to the first side of the package substrate, and a backside warpage control structure embedded in the package substrate from the second side of the package substrate. The front-side warpage control structure includes a first disconnected structure and a second disconnected structure laterally separated from each other by a gap. The backside warpage control structure includes a third disconnected structure and a fourth disconnected structure laterally separated from each other.

Integrated circuit package and method of forming same

A semiconductor device and manufacturing process are provided wherein a first semiconductor device is electrically connected to redistribution structures. An antenna structure is located on an opposite side of the first semiconductor device from the redistribution structures, and electrical connections separate from the first semiconductor device connect the antenna structure to the redistribution structures.

A method includes joining a first wafer to a second wafer, forming a first through-via penetrating through the first wafer and further extending into the second wafer, and forming a redistribution line on the first wafer. The redistribution line and the first through-via electrically connect a first conductive feature in the first wafer to a second conductive feature in the second wafer. An electrical connector is formed over the first wafer.

3D stacking architecture through TSV and methods forming same

A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.

Package structure

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

Semiconductor package including a semiconductor die disposed in a cavity and method for manufacturing thereof

A semiconductor structure includes a fan-out package comprising at least one semiconductor die, a redistribution structure including fan-out bonding pads, and a first underfill material portion located between the at least one semiconductor die and the redistribution structure; a packaging substrate comprising chip-side bonding pads; an array of solder material portions bonded to the chip-side bonding pads and the fan-out bonding pads; a second underfill material portion laterally surrounding the array of solder material portions; and at least one buffer block structure located between a respective neighboring pair of solder material portions within the array of solder material portions and between the fan-out package and the packaging substrate, and laterally surrounded by the second underfill material portion.

Buffer block structures for C4 bonding and methods of using the same

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Hsinchu, Taiwan

Shin-Puu Jeng