Taiwan Semiconductor Manufacturing Comp. Ltd.

Applied Materials, Inc.

Shin-Puu Jeng

Po-Yao Lin

Chen-Hua Douglas Yu

Shu-Shen Yeh

Shang-Yun Hou

Feng-Cheng Hsu

Shuo-Mao Chen

Chin-Hua Wang

Po-Yao Chuang

Hsien-Wei Chen

Ming-Chih Yew

Po-Hao Tsai

Wen-Chih Chiou

Jing-Cheng Lin

Yu-Sheng Lin

Chia-Kuei Hsu

Po-Chen Lai

Hao-Yi Tsai

Techi Wong

Wei-Cheng Wu

Jui-Pin Hung

Hsien-Pin Hu

Der-Chyang Yeh

Hsien-Wen Liu

Kim Hong Chen

Wensen Hung

Cheng-Chieh Hsieh

Wai-Fan Yau

David Wingto Cheung

Yi-Wen Wu

Cheng-Lin Huang

Szu Wei Lu

Chi-Hsi Wu

Tzuan-Horng Liu

Kuo-Ching Hsu

Yung-Cheng Lu

Ying-Ching Shih

An-Jhih Su

Farhad K Moghadam

Michael S Barnes

Tetsuya Ishikawa

Robert Parkash Mandal

Szu-Wei Lu

Ying-Ju Chen

Hsueh-Chung Chen

Hsiao-Wen Lee

Chia-Lun Tsai

Jie Chen

Tsang-Jiuh Wu

Ming-Yen Chiu

Li-Hsien Huang

Weng-Jin Wu

Ku-Feng Yang

Chih-Hsien Lin

Hsiao-Tsung Yen

Chih-Wei Wu

Cheng-Hsien Hsieh

Li-Qun Xia

Ellie Y Yieh

Ching-Wen Hsiao

Chien-Hung Chen

Chih-Hang Tung

Mill-Jer Wang

Bruce C S Chou

Yi-Li Hsiao

Chung-Shi Liu

Mirng-Ji Lii

Chao-Wen Shih

Chi-I Lang

Pei-Haw Tsao

Chin-Fu Kao

Hsin-Hui Lee

Li-Han Hsu

Chin-Chuan Chang

Yuan-Hung Liu

Chen-Shien Chen

Hung-Jui Kuo

Chenming Hu

Chih-Hua Chen

Chen-Cheng Kuo

Chien-Hung Zordius Chen

Hsin-Yu Chen

Ming Hung Tseng

Tsung-Yu Chen

Jyh-Cherng Sheu

Chun-Jen Chen

Ming-Fa Chen

Carlos H Diaz

Srinivas D Nemani

Kong-Beng Thei

Shankar Venkataraman

Tsung-Shu Lin

Chun-Hung Chen

Chine-Gie Lou

Chin-Yu Ku

Harry Hak-Lay Chuang

Yi-Ming Sheu

Hsi-Kuei Cheng

Chien-Hsiun Lee

Jian-Hong Lin

A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

Semiconductor device and method of manufacture

A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate supporting and electrically connected to the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment connected to the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.

Semiconductor die package with conductive line crack prevention design

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure over the wiring substrate. The chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. The heat-spreading lid includes a ring structure and a top plate, the ring structure surrounds the first chip structure, the top plate covers the ring structure and the first chip structure, and the first chip structure has a first sidewall and a second sidewall opposite to the first sidewall.

Chip package structure with lid

Provided is a package structure including a substrate, a stiffener ring, an eccentric die, a lid layer, and a buffer layer. The stiffener ring is disposed on the substrate. The stiffener ring has an inner perimeter to enclose an accommodation area. The eccentric die is disposed within the accommodation area on the substrate. The eccentric die is offset from a center of the accommodation area to close to a first side of the stiffener ring. The lid layer is disposed on the stiffener ring and overlays the eccentric die. The buffer layer is embedded in the lid layer between the first side of the stiffener ring and the eccentric die. The buffer layer has a thickness less than a thickness of the lid layer.

Package structure with buffer layer embedded in lid layer

Semiconductor packages and methods of fabricating semiconductor packages include a package substrate having a recess formed in a surface of the package substrate and at least one channel in a bottom surface of the recess. The recess may be configured to accommodate a semiconductor device located over a surface of an interposer that is bonded to the package substrate. Accordingly, a minimum gap distance may be maintained between the semiconductor device and the package substrate, which may ensure that sufficient underfill material may flow between the semiconductor device and the package substrate and within the at least one channel, thereby improving of the structural coupling between the interposer and the package substrate, and reducing the likelihood of package defects, such as delamination, cracking, and/or popcorn defects.

Semiconductor package with substrate recess and methods for forming the same

Three dimensional structures and methods are provided in which capacitors are formed separately from a first semiconductor device and then connected to the first semiconductor device. For example, a capacitor chip is provided and then bonded to a first semiconductor die. The capacitor chip and the first semiconductor die are encapsulated with a first encapsulant, and one of the capacitor chips and the first semiconductor die are thinned to expose through vias.

Semiconductor devices and methods of manufacture

A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Multi-chip device and method of formation

A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. The plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package.

Packages with metal line crack prevention design

A semiconductor structure includes a fan-out package comprising at least one semiconductor die, a redistribution structure comprising fan-out bonding pads, and a first underfill material portion, a packaging substrate comprising chip-side bonding pads, solder material portions bonded to the chip-side bonding pads and the fan-out bonding pads, a second underfill material portion laterally surrounding the solder material portions, and at least one cushioning film located on the packaging substrate and contacting the second underfill material portion and having a Young's modulus that is lower than a Young's modulus of the second underfill material portion.

Underfill cushion films for packaging substrates and methods of forming the same

A manufacturing method of a semiconductor package includes the following steps. A first semiconductor device is provided over a substrate, wherein the first semiconductor device is offset toward an edge of the substrate. A ring structure is attached to the substrate by a first adhesive layer, wherein the ring structure surrounds the first semiconductor device and comprises an overhang portion cantilevered over the edge of the substrate. A lid structure is attached to the ring structure by a second adhesive layer, wherein the lid structure covers the first semiconductor device and comprises an extending portion covering the overhang portion.

Manufacturing method of semiconductor package

In an embodiment, a package including: a redistribution structure including a first dielectric layer and a first conductive element disposed in the first dielectric layer; a first semiconductor device bonded to the redistribution structure, wherein the first semiconductor device includes a first corner; and an underfill disposed over the redistribution structure and including a first protrusion extending into the first dielectric layer of the redistribution structure, wherein the first protrusion of the underfill overlaps the first corner of the first semiconductor device in a plan view.

Package and method for forming the same

A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure. The global shielding structure is surrounding the first insulating encapsulant, the second insulating encapsulant, and covering sidewalls of the redistribution structure.

Package structure

A method of forming a semiconductor structure includes the following operations. First deep vias are formed in a first glass layer. A first redistribution layer structure is formed on a first side of the first glass layer, and the first redistribution layer structure is electrically connected to the first deep vias. A carrier is bonded to the first redistribution layer structure. The first glass layer is grinded until surfaces of the first deep vias are exposed. A second redistribution layer structure is formed on a second side of the first glass layer opposite to the first side, and the second redistribution layer structure is electrically connected to the first deep vias.

Semiconductor structures including glass core layer and methods of forming the same

Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

Multi-chip packages and methods of forming the same

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip package over the wiring substrate. The chip package structure includes a first heat conductive structure over the chip package. The chip package structure includes a ring dam over the chip package and surrounding the first heat conductive structure. The ring dam has a gap. The chip package structure includes a heat dissipation lid over the first heat conductive structure and the ring dam.

Chip package structure with ring dam

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Hsinchu, Taiwan

Shin-Puu Jeng