Taiwan Semiconductor Manufacturing Comp. Ltd.

Applied Materials, Inc.

Shin-Puu Jeng

Po-Yao Lin

Chen-Hua Douglas Yu

Shu-Shen Yeh

Shang-Yun Hou

Feng-Cheng Hsu

Chin-Hua Wang

Shuo-Mao Chen

Po-Yao Chuang

Hsien-Wei Chen

Ming-Chih Yew

Po-Hao Tsai

Wen-Chih Chiou

Chia-Kuei Hsu

Jing-Cheng Lin

Yu-Sheng Lin

Po-Chen Lai

Hao-Yi Tsai

Techi Wong

Wei-Cheng Wu

Jui-Pin Hung

Der-Chyang Yeh

Hsien-Pin Hu

Hsien-Wen Liu

Kim Hong Chen

Wensen Hung

Cheng-Chieh Hsieh

Wai-Fan Yau

David Wingto Cheung

Yi-Wen Wu

Cheng-Lin Huang

Kuo-Ching Hsu

Szu Wei Lu

Chi-Hsi Wu

Tzuan-Horng Liu

Yung-Cheng Lu

Ying-Ching Shih

An-Jhih Su

Farhad K Moghadam

Michael S Barnes

Tetsuya Ishikawa

Robert Parkash Mandal

Jie Chen

Sao-Ling Chiu

Szu-Wei Lu

Ying-Ju Chen

Hsueh-Chung Chen

Hsiao-Wen Lee

Chia-Lun Tsai

Tsang-Jiuh Wu

Ming-Yen Chiu

Li-Hsien Huang

Weng-Jin Wu

Ku-Feng Yang

Chih-Hsien Lin

Hsiao-Tsung Yen

Chih-Wei Wu

Cheng-Hsien Hsieh

Li-Qun Xia

Ellie Y Yieh

Ching-Wen Hsiao

Chien-Hung Chen

Chih-Hang Tung

Mill-Jer Wang

Bruce C S Chou

Yi-Li Hsiao

Chung-Shi Liu

Mirng-Ji Lii

Chao-Wen Shih

Chi-I Lang

Pei-Haw Tsao

Chin-Fu Kao

Hsin-Hui Lee

Li-Han Hsu

Chin-Chuan Chang

Chen-Shien Chen

Hung-Jui Kuo

Chenming Hu

Chih-Hua Chen

Chen-Cheng Kuo

Chien-Hung Zordius Chen

Hsin-Yu Chen

Ming Hung Tseng

Tsung-Yu Chen

Jyh-Cherng Sheu

Chun-Jen Chen

Ming-Fa Chen

Carlos H Diaz

Srinivas D Nemani

Kong-Beng Thei

Shankar Venkataraman

Tsung-Shu Lin

Chun-Hung Chen

Chine-Gie Lou

Chin-Yu Ku

Harry Hak-Lay Chuang

Yi-Ming Sheu

Hsi-Kuei Cheng

Sheng-Chen Chung

Chien-Hsiun Lee

A method includes joining a first wafer to a second wafer, forming a first through-via penetrating through the first wafer and further extending into the second wafer, and forming a redistribution line on the first wafer. The redistribution line and the first through-via electrically connect a first conductive feature in the first wafer to a second conductive feature in the second wafer. An electrical connector is formed over the first wafer.

3D stacking architecture through TSV and methods forming same

A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.

Package structure

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

Semiconductor package including a semiconductor die disposed in a cavity and method for manufacturing thereof

A semiconductor structure includes a fan-out package comprising at least one semiconductor die, a redistribution structure including fan-out bonding pads, and a first underfill material portion located between the at least one semiconductor die and the redistribution structure; a packaging substrate comprising chip-side bonding pads; an array of solder material portions bonded to the chip-side bonding pads and the fan-out bonding pads; a second underfill material portion laterally surrounding the array of solder material portions; and at least one buffer block structure located between a respective neighboring pair of solder material portions within the array of solder material portions and between the fan-out package and the packaging substrate, and laterally surrounded by the second underfill material portion.

Buffer block structures for C4 bonding and methods of using the same

A bonded assembly including a first structure and a second structure is provided. The first structure includes first metallic connection structures surrounded of which a passivation dielectric layer includes openings therein, and first metallic bump structures having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane including a distal horizontal surface of the passivation dielectric layer. The second structure includes second metallic bump structures having a respective second horizontal bonding surface segment that protrudes toward the first structure. The first metallic bump structures is bonded to the second metallic bump structures through solder material portions.

Bridging-resistant microbump structures and methods of forming the same

A structure includes a first package component including a first conductive pad, and a second package component overlying the first package component. The second package component includes a surface dielectric layer, and a conductive bump protruding lower than the surface dielectric layer. The first conductive bump includes a first sidewall facing away from a center of the first package component, and a second sidewall facing toward the center. A solder bump joins the first conductive pad to the first conductive bump. The solder bump contacts the first sidewall. An underfill is between the first package component and the second package component, and the underfill contacts the second sidewall.

Bump joint structure with distortion and method forming same

A semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, where the package includes: an interposer, where a first side of the interposer is bonded to the first surface of the substrate through first conductive bumps; dies attached to a second side of the interposer opposing the first side; and a molding material on the second side of the interposer around the dies; a plurality of thermal interface material (TIM) films on a first surface of the package distal from the substrate, where each of the TIM films is disposed directly over at least one respective die of the dies; and a heat-dissipation lid attached to the first surface of the substrate, where the package and the plurality of TIM films are disposed in an enclosed space between the heat-dissipation lid and the substrate, where the heat-dissipation lid contacts the plurality of TIM films.

High efficiency heat dissipation using discrete thermal interface material films

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes an interposer substrate over the wiring substrate. The interposer substrate includes a redistribution structure, a dielectric layer, a conductive via, and a plurality of first dummy vias, the dielectric layer is over the redistribution structure, the conductive via and the first dummy vias pass through the dielectric layer, the first dummy vias surround the conductive via, and the first dummy vias are electrically insulated from the wiring substrate. The chip package structure includes a chip structure over the interposer substrate. The chip structure is electrically connected to the conductive via, and the chip structure is electrically insulated from the first dummy vias.

Method for forming chip package structure

A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

Semiconductor device and method of manufacture

A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate supporting and electrically connected to the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment connected to the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.

Semiconductor die package with conductive line crack prevention design

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure over the wiring substrate. The chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. The heat-spreading lid includes a ring structure and a top plate, the ring structure surrounds the first chip structure, the top plate covers the ring structure and the first chip structure, and the first chip structure has a first sidewall and a second sidewall opposite to the first sidewall.

Chip package structure with lid

Provided is a package structure including a substrate, a stiffener ring, an eccentric die, a lid layer, and a buffer layer. The stiffener ring is disposed on the substrate. The stiffener ring has an inner perimeter to enclose an accommodation area. The eccentric die is disposed within the accommodation area on the substrate. The eccentric die is offset from a center of the accommodation area to close to a first side of the stiffener ring. The lid layer is disposed on the stiffener ring and overlays the eccentric die. The buffer layer is embedded in the lid layer between the first side of the stiffener ring and the eccentric die. The buffer layer has a thickness less than a thickness of the lid layer.

Package structure with buffer layer embedded in lid layer

Semiconductor packages and methods of fabricating semiconductor packages include a package substrate having a recess formed in a surface of the package substrate and at least one channel in a bottom surface of the recess. The recess may be configured to accommodate a semiconductor device located over a surface of an interposer that is bonded to the package substrate. Accordingly, a minimum gap distance may be maintained between the semiconductor device and the package substrate, which may ensure that sufficient underfill material may flow between the semiconductor device and the package substrate and within the at least one channel, thereby improving of the structural coupling between the interposer and the package substrate, and reducing the likelihood of package defects, such as delamination, cracking, and/or popcorn defects.

Semiconductor package with substrate recess and methods for forming the same

Three dimensional structures and methods are provided in which capacitors are formed separately from a first semiconductor device and then connected to the first semiconductor device. For example, a capacitor chip is provided and then bonded to a first semiconductor die. The capacitor chip and the first semiconductor die are encapsulated with a first encapsulant, and one of the capacitor chips and the first semiconductor die are thinned to expose through vias.

Semiconductor devices and methods of manufacture

A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Multi-chip device and method of formation

Growing community of inventors

Hsinchu, Taiwan

Shin-Puu Jeng