Samsung Electronics Co., Ltd.

Shin-Jae Kang

Gyu-Hwan Oh

In-Sun Park

Gyuhwan Oh

Hyunseok Lim

Nak-Hyun Lim

Do-Hyung Kim

Jongchul Park

Hyun-Suk Lee

Byoung-Jae Bae

Jong-Chul Park

Hyun-seok Lim

Byoungjae Bae

Kyung-Tae Jang

Young-Seok Choi

Tai-Soo Lim

Jiyoon Chung

Junyeon Hwang

Dong-Hyun Im

In-Jae Lee

Insun Park

Eunsun Noh

Jeon-Il Lee

Dong-Hoon Han

Hyun-Seok Lim

Kyung Rae Byun

Seok-Yeong Jung

Sug-woo Jung

Hyunsoo Shin

Chan-Mi Lee

Chae-mook Lim

Sun-Soo Lee

Kevin Bae

Jeong-Hyun Ha

Kyung-Wook Park

Jaesuk Kwon

In a layer deposition method, a substrate is loaded into a process chamber. A gas filling tank is charged with a gas to a predetermined charge pressure. The pressure of the gas is elevated to a pressure greater than the predetermined charge pressure. The gas is introduced into the process chamber.

Layer deposition method and layer deposition apparatus

Variable resistance memory devices are provided. A variable resistance memory device includes conductive lines and a memory cell including a variable resistance element on one of the conductive lines. The variable resistance memory device includes a first insulating region between the conductive lines. Moreover, the variable resistance memory device includes a second insulating region on the first insulating region between the conductive lines. Methods of forming variable resistance memory devices are also provided.

Variable resistance memory devices, and methods of forming variable resistance memory devices

Disclosed is an electronic device including: at least one processor; and a memory electrically connected to the at least one processor, wherein the memory stores instructions to recognize a received first voice, recognizes a first speaker based on the recognized first voice, and determines a response corresponding to the first voice based on a result of the recognition of the first speaker. Other embodiments are possible.

Method of responding to input voice of electronic device and electronic device therefor

In a method of manufacturing an MRAM device, a lower electrode and a preliminary first free layer pattern sequentially stacked are formed on a substrate. An upper portion of the preliminary first free layer pattern is removed to form a first free layer pattern. A second free layer and a tunnel barrier layer are sequentially formed on the first free layer pattern. The second free layer is partially oxidized to form a second free layer pattern. A fixed layer structure is formed on the tunnel barrier layer.

Magnetoresistive random access memory device

A method of fabricating a magnetic memory device is provided. The method may include sequentially forming a first magnetic layer, a tunnel barrier layer, and a second magnetic layer on a substrate, forming a mask pattern on the second magnetic layer to expose a portion of the second magnetic layer, forming a capping insulating layer on a sidewall of the mask pattern and the portion of the second magnetic layer, injecting an oxygen ion into the portion of the second magnetic layer through the capping insulating layer to form an oxide layer, anisotropically etching the capping insulating layer to form a capping spacer, and patterning the oxide layer, the tunnel barrier layer, and the first magnetic layer using the mask pattern and the capping spacer.

Magnetic memory device comprising oxide patterns

Magnetoresistive random access memory device and method of manufacturing the same

Magnetic memory devices include a plurality of first magnetic patterns on a substrate so as to be spaced apart from each other, a first insulating pattern between the first magnetic patterns to define the first magnetic patterns, and a tunnel barrier layer covering the first magnetic patterns and the first insulating pattern. The first insulating pattern includes a first magnetic element, and the first magnetic element is the same as a second magnetic element constituting the first magnetic patterns.

Magnetic memory devices

A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.

Semiconductor memory device including buffer electrode

Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.

Semiconductor device and method for forming the same

Semiconductor device and method of forming the same

The present invention provides methods of forming a phase-change material layer including providing a substrate and a chalcogenide target including germanium (Ge), antimony (Sb) and tellurium (Te) at a temperature wherein tellurium is volatilized and antimony is not volatilized, and performing a sputtering process to form the phase-change material layer including a chalcogenide material on the substrate. Methods of manufacturing a phase-change memory device using the same are also provided.

Methods of forming a phase-change material layer including tellurium and methods of manufacturing a phase-change memory device using the same

Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming an ohmic layer on an upper surface of a conductive structure and extending away from the structure along at least a portion of a sidewall of an opening in an insulation layer. An electrode layer is formed on the ohmic layer. A variable resistivity material is formed on the insulation layer and electrically connected to the electrode layer.

Variable resistance non-volatile memory cells and methods of fabricating same

Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming a cup-shaped electrode on sidewalls of an opening in an insulation layer and through the opening on an ohmic layer that is stacked on a conductive structure. An insulation filling member is formed that at least partially fills an interior of the electrode. The insulation filling member is formed within a range of temperatures that is sufficiently low to not substantially change resistance of the ohmic layer. A variable resistivity material is formed on the insulation filling member and is electrically connected to the electrode.

Growing community of inventors

Seoul, South Korea

Shin-Jae Kang