Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Dongwoo Fine-chem Co., Ltd.

Shin-Il Choi

Yu-Gwang Jeong

Sang-Gab Kim

Hong-Kee Chin

Seung-Ha Choi

Dong-Ju Yang

Ki-Yeup Lee

Min-Seok Oh

Bong-Kyun Kim

Ji-Young Park

Sung-Hoon Yang

Byeong-Beom Kim

Jean-Ho Song

Jung-Suk Bang

Yun-Jong Yeo

Su-Bin Bae

Ji-Hyun Kim

Jang-Soo Kim

Ki-Hun Jeong

Woo-Geun Lee

Young-Wook Lee

Ji-Sun Kim

Jong-Hyun Choung

Yeong-Keun Kwon

Kap-Soo Yoon

Yang-Ho Bae

Seung-Hwan Shim

Jae-Neung Kim

Seung-Ho Yoon

Jae-Hong Kim

Hong-Sick Park

Dae-Ho Kim

Jong-in Kim

Shi-Yul Kim

Sang-tae Kim

Jae-Hyoung Youn

Joo-han Kim

Ho-Jun Lee

Sun-Young Hong

Sung-Ryul Kim

Hee-Joon Kim

Hwa-Yeul Oh

Woong-Kwon Kim

Yeo-Geon Yoon

Chang-Hoon Kim

Yong-Mo Choi

Young-Chul Park

Seon-Il Kim

O-Sung Seo

In-Ho Yu

Suck-Jun Lee

Joon-Woo Lee

Sang-Hoon Jang

Je-Hyeong Park

Young-Jun Jin

Ki-Yong Song

O-Byoung Kwon

Min-Ki Lim

Nam-Seok Suh

Pil-Soon Hong

Sung-Hen Cho

Dong-Hoon Lee

Sang Gab Kim

Yu-Jin Lee

Byung-Uk Kim

Pil-Sang Yun

Jung-Ha Son

Yong-Hwan Ryu

Tae-Woo Kim

Wang-Woo Lee

Myoung-Geun Cha

Young-Jin Yoon

Yu Gwang Jeong

Jong-Hyun Jeong

Suk-Il Yoon

Kyong-Min Kang

Dong-Ki Kim

Sun-Joo Park

Seok-Jun Jang

Soon-Beom Hur

Chang-Ho Jeong

A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.

Display substrate comprising a plurality of conductive patterns

According to an exemplary embodiment, a display substrate includes a gate metal pattern comprising a gate electrode, an active pattern disposed on the gate pattern and a source metal pattern disposed on the active pattern. The source metal pattern includes a first lower pattern disposed on the active pattern, a second lower pattern disposed on the first lower pattern, a low-resistance metal pattern disposed on the second lower pattern, and an upper pattern disposed on the low-resistance metal pattern. The first lower pattern, the second lower pattern, and the upper pattern each include a material that is the same.

Display substrate capable of decreasing defects and the method of the same

Display substrate and method of manufacturing the same

A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer.

Thin film transistor substrate

Thin film transistor substrate and method of fabricating the same

A display substrate includes a base substrate, a common line on the base substrate, a first insulation layer covering the common line and having a first insulating material, a conductive pattern on the first insulation layer and including a source electrode and a drain electrode, a second insulation layer covering the drain electrode and the common line, and including a lower second insulation layer having a second insulating material and an upper second insulation layer having the first insulating material, a first electrode electrically connected to the drain electrode through a first contact hole in the second insulation layer, and a second electrode electrically connected to the common line through a second contact hole in the first and second insulation layers. The upper and lower second insulation layers on the drain electrode have a first hole and a second hole respectively that form the first contact hole.

Display substrate and method of manufacturing the display substrate

A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Thin film transistor substrate and the method thereof

A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.

Contact portion of wire and manufacturing method thereof

A display apparatus includes: a substrate defining transistor and wiring areas; a thin film transistor in the transistor area and including a gate electrode, an active layer, and source and drain electrodes; an etch prevention layer in the transistor area, absent in the wiring area and covering the active layer, and first and second contact holes defined in the etch prevention layer and through which the active layer is electrically coupled to the source and drain electrodes; a first wiring layer in the wiring area; a first insulating layer which covers the gate electrode and the first wiring layer, and a third contact hole defined in the first insulating layer in the wiring area and exposing the first wiring layer; and a second wiring layer on the first insulating layer and in the wiring area, and electrically coupled to the first wiring layer via the third contact hole.

Display apparatus and method of manufacturing the same

A display substrate includes a data pad on a base substrate, a first buffer layer which covers the data pad, a second buffer layer pattern which is disposed on the first buffer layer and separated from the data pad in a plan view, an active layer on the second buffer layer pattern, a gate insulation layer pattern on the active layer, both ends of the active layer exposed by the gate insulation layer pattern, and a gate electrode on the gate insulation layer pattern.

Display substrates, methods of manufacturing the same and display devices including the same

A method of manufacturing a display substrate includes forming a gate insulation layer on the base substrate on which a gate metal pattern, forming a data metal pattern on the gate insulation layer, sequentially forming a insulation layer and an organic layer on the base substrate on which the data metal pattern is formed, partially exposing the organic layer, developing the organic layer to partially remove the organic layer on the data metal pattern and to expose at least a portion of the protecting layer on the gate metal pattern, forming a common electrode on the organic layer, forming a pixel electrode on the on the organic layer, and forming an insulation layer between the pixel electrode and the common electrode. An etching degree of a data metal may be controlled by controlling a thickness of a remained organic layer to reduce a damage of the data metal.

Exemplary embodiments of the present invention disclose a non-halogenated etchant for etching an indium oxide layer and a method of manufacturing a display substrate using the non-halogenated etchant, the non-halogenated etchant including nitric acid, sulfuric acid, a corrosion inhibitor including ammonium, a cyclic amine-based compound, and water.

Non-halogenated etchant and method of manufacturing a display substrate using the non-halogenated etchant

Growing community of inventors

Hwaseong-si, South Korea

Shin-Il Choi