Kabushiki Kaisha Toshiba

Shin-ichi Taka

Jiro Ohshima

Hiroshi Naruse

Koji Kimura

Masaharu Aoyama

Toshiyo Motozima

Kuniaki Kumamaru

Kouji Kimura

Masahiro Abe

Nobuyuki Itoh

Toshio Yamaguchi

Hiroomi Nakajima

Yasuhiro Katsumata

Hiroyuki Nihira

Kenji Hirakawa

Hideki Takada

Eiryo Tsukioka

Toshiyo Ito

Jiro Oshima

Manufacturing a double polysilicon layer self-aligned type bipolar transistor. A polysilicon layer for emitter impurity diffusion is formed prior to the formation of a polysilicon layer for leading out a base. A first polysilicon layer containing impurities for base impurity diffusion is deposited over the entire surface of a semiconductor structure. After the first polysilicon layer is patterned into a predetermined shape, an intrinsic base layer is formed by thermally diffusing impurities from a base impurity diffusion source. Subsequently, a second polysilicon layer containing emitter impurities is formed over the base impurity diffusion source, and then patterning is performed such that the first and second polysilicon layers remain in a region narrower than the base impurity diffusion source. Thereafter, an emitter layer is formed by thermal diffusion.

Method for manufacturing self-aligned bipolar transistors using double

The specification discloses a hetero bipolar transistor which comprises a semiconductor substrate, a first silicon layer serving as a collector, a first silicon-germanium layer serving as a base, a second silicon layer serving as a collector, and a second silicon-germanium layer. A side wall of the second silicon-germanium layer is in contact with side walls of the first silicon layer, the first silicon-germanium layer and the second silicon layer. The second silicon-germanium layer is disposed to surround the first silicon layer, the first silicon-germanium layer, and the second silicon layer, and has an energy band gap substantially the same as that of the first silicon-germanium layer.

Method of manufacturing a hetero bipolar transistor

Hetero bipolar transistor and method of manufacturing the same

A semiconductor integrated circuit according to the present invention comprises a semiconductor substrate, a plurality of MOS field effect transistors each formed on a surface region of the semiconductor substrate and having source and drain regions, a gate insulating film formed on a region between the source and drain regions, and a gate electrode formed on the gate insulating film. The gate electrode includes a polycrystalline SiGe-mixed crystal which is expressed by Si.sub.1-x Ge.sub.x (1&gt;x&gt;0).

Method for manufacturing semiconductor integrated circuit device

According to this invention, in a method of manufacturing a bipolar transistor, a first oxide film, a nitride film, a first polysilicon film containing boron, and a second oxide film are formed on a substrate. A first opening is formed in the second oxide film and the first polysilicon film. The nitride film and the first oxide film are etched in and near the first opening to form overhung portions between the substrate and the first semiconductor film around the first opening. A second polysilicon film for burying the overhung portions is formed on the entire surface of the resultant structure. Thereafter, boron in the second polysilicon film is thermally diffused in the substrate to form an external base region and a link region. The second polysilicon film is etched to leave the second polysilicon film at only the overhung portions. After an internal base region formed in the substrate. Thereafter, an emitter region formed in the internal base region.

Method of manufacturing bipolar transistor operated at high speed

In the method of manufacturing a semiconductor device, a buffer oxide film, an oxidation-resistant film and a first poly-Si film containing a p-type impurity are successively formed to form a laminate structure on the n-type collector region, followed by forming a protective oxide film by CVD. Then, an opening portion reaching the oxidation-resistant film is formed, followed by forming a second protective insulation film to cover the surface of the first poly-Si film exposed at the side wall of the opening portion. The oxidation-resistant film is excessively etched using the protective insulation films as an etching mask so as to expose the buffer oxide film and to form a bore below the first poly-Si film. The exposed buffer oxide film is removed, followed by filling the bore with a second poly-Si film. Then, a heat treatment is performed under an oxidative atmosphere to form a thermal oxide film covering the surface of the second poly-Si film. At the same time, the p-type impurity contained in the first poly-Si film is diffused through the second poly-Si film into the collector region to form a p-type outer base region. Further, a p-type inner base region, n-type emitter region and an emitter electrode are formed.

Method of manufacturing semiconductor device

A bipolar transistor includes a p-type external base region formed on the major surface of an n-type semiconductor substrate, a plurality of p-type internal base regions formed to be surrounded by the external base region, and emitter regions of a first conductivity type respectively formed in the internal base regions. An oxide film and a nitride film, stacked on each other, extend outward from an outer peripheral portion of the external base region on the major surface of the semiconductor substrate, and define openings therein. A p-type semiconductor film is formed on the external base region in the openings. A first conductive layer having a p-type semiconductor is formed on the nitride film and the semiconductor film. Side-wall-like oxide films are formed on side wall portions, of the semiconductor film and the first conductive layer, opposite to the emitter regions. A second conductive layer having an n-type semiconductor and serving as an emitter electrode extraction portion is formed on the side-wall-like oxide films to be in contact with the emitter regions.

Bipolar transistor

According to the method of manufacturing a semiconductor device of the present invention, an insulation film is formed on a silicon substrate, and a resist film having a predetermined pattern is formed on the insulation film, followed by forming an opening on the insulation film with the resist film performing as a mask. Then, an impurity having conductivity are implanted into said silicon substrate with the resist film performing as a mask and silicon ions are implanted into the silicon substrate with the resist film performing as a mask. After that, the resist film is removed. Further, a refractory metal film which covers at least the opening is formed. Moveover, a diffusion layer which causes electrical activation of the impurity having conductivity is formed by annealing, followed by formation a silicide layer at where the surfaces of the silicon substrate and the metal film meet.

Method of manufacturing a semiconductor device having a silicide layer

This invention discloses a method of manufacturing an SST bipolar transistor, and the manufacturing method is capable of defining the size of a base region of the SST bipolar transistor. An insulating film and a spacer film serving as a spacer are sequentially formed in a bipolar transistor forming region on the main surface of a semiconductor substrate. Thereafter, the spacer film is patterned into a spacer film pattern for defining the size of the base region. A second insulating film, a base electrode pattern and a third insulating film are sequentially formed on the spacer film pattern. A first opening which reaches the spacer film pattern through the second insulating film, the base electrode pattern and the third insulating film is formed. The spacer film pattern is etched from the first opening to form a second opening having a diameter larger than that of the first opening. The insulating film exposed in the second opening is etched. The size of the base region on the major surface of the semiconductor substrate is defined by the size of the second opening.

Method of manufacturing super self-alignment technology bipolar

In the invention, the width of the emitter contact layer is determined in accordance with the width of a first side wall, and the junction distance between a base contact layer and the emitter contact layer is determined in accordance with the width of a second side wall. The junction distance between the emitter contact layer and the base contact layer can be decreased, no extra high-temperature annealing such as thermal oxidation is needed, and the diffusion profile can be controlled to be shallow.

A metal layer is formed by selective CVD method on an emitter region formed by using a field oxide film as a mask. Opening for ion-implanting an impurity for forming external base region is formed in the field oxide film by utilizing the metal layer and a metal layer creep up a bird's beak of the field oxide film as masks. An impurity is doped in a semiconductor substrate through the opening formed in the field oxide film to form external base region. The distance between the emitter region and external base region is controlled by a length of the metal layer creep up the bird's beak.

Method of manufacturing bipolar transistor with self-aligned external

A transistor is formed according to the solid phase epitaxial growth which is one of the semiconductor integrated circuit device manufacturing techniques. A low-concentration impurity region is formed by selective solid phase epitaxial growth instead of using an epitaxial substrate. The solid phase epitaxial growth is performed twice, when a collector region is formed and when a base region is formed. The depth of collector and base regions are determined by the thickness of the solid phase growth layers, respectively.

Method of manufacturing semiconductor integrated circuit device having

In a method of manufacturing a semiconductor device according to the present invention, a given position of a thermal oxide film formed on a monocrystalline silicon layer is opened to expose a surface of the monocrystalline silicon layer to serve as a getter site, a polycrystalline silicon layer is deposited on the thermal oxide film and the surface of the monocrystalline silicon layer, and the polycrystalline silicon layer is oxidized to convert the surface of the monocrystalline silicon layer directly contacting the polycrystalline silicon layer into an oxide film by thermal oxidation. That is, the position of interface between the oxide film and the monocrystalline silicon layer is shifted into the original monocrystalline silicon layer. During thermal oxidation of the polycrystalline silicon layer, a plurality of crystal defects to serve as getter sites are generated deeper than those generated by a conventional implagetter method in the monocrystalline silicon layer. In addition, the crystal defects generated in the manner described above do not extend to the surrounding region by subsequent annealing so that a region of the crystal defects is limited.

Method of gettering a semiconductor device and forming an isolation

A method of manufacturing a semiconductor device, comprising the steps of sequentially forming a buried region and an epitaxial layer on a major surface of a semiconductor substrate, forming a conductive layer along an annular trench extending to the buried region, filling the annular trench with an insulating material and forming a functional element in said epitaxial layer surrounded by said buried region and said insulating material within said annular trench. In this method, the step of forming the conductive layer along the annular trench is carried out by the steps of forming an annular trench extending through said buried region, and depositing a conductive layer on only a side wall surface of said annular trench.

Growing community of inventors

Yokosuka, Japan

Shin-ichi Taka