Kabushiki Kaisha Toshiba

Shin-ichi Imai

Akira Sakata

Naoki Hosoya

Katsuji Fujita

Atsuhiko Nunokawa

Tatsuya Yoshie

A TAB film comprises a resin film and a plurality of leads provided on the resin film to extend from a side of the resin film, each of the plurality of leads having a bonding portion at an end portion, the plurality of leads providing a plurality of multilevel structure for every adjacent two leads at an extended portion extending from the side of the resin film so as to expose the bonding portion of each of the adjacent two leads.

Semiconductor device having multilevel tab leads

In a clamping circuit comprising a voltage comparator for comparing an input signal voltage supplied to the signal input terminal and a reference voltage, a clamping circuit of the present invention comprises a bias voltage supplying circuit and a switch circuit inserted between the bias voltage supplying circuit and the signal input terminal. The input signal voltage is compared with the reference voltage by the voltage comparator, and the switch circuit is ON/OFF-controlled on the basis of the comparison result. When the switch circuit is enabled, a bias voltage supplying circuit is supplied to the signal input terminal, and the input signal voltage is clamped at a voltage equal to the reference voltage. When the switch circuit comprises a CMOS transfer gate, a voltage drop does not occur across the switch circuit regardless of the value of the bias voltage.

Clamping circuit

An input bias circuit employs a gate input type CCD register and an inversion-type amplifier. An output node of the inversion-type amplifier is connected to the input gate electrode of the CCD register, and an input signal to be biased is supplied to the input gate electrode. An output node of the inversion-type amplifier is connected to the floating diffusion region of the CCD register, and a signal charge is picked up from the floating diffusion region. A comparator performs comparison among the low level of the injection pulse supplied to the input diffusion region (which serves as an input diode), the potential level of the input signal supplied to the input gate electrode of the CCD register, and the level of the low-level generated by a low-level signal generating means. On the basis of this comparison, the potential level of the input signal of the CCD register is controlled such that it is higher than the low level of the injection pulse.

Input bias circuit for gate input type charge transfer device for

In a clamping circuit comprising a voltage comparator for comparing an input signal voltage supplied to the signal input terminal and a reference voltage, a clamping circuit of the present invention comprises a bias voltage supplying circuit and a switch circuit inserted between the bias voltage supplying circuit and the signal input terminal. The input signal voltage is compared with the reference voltage by the voltage comparator, and the switch circuit is ON/OFF-controlled on the basis of the comparison result. When the switch circuit is enabled, a bias voltage of the bias voltage supplying circuit is supplied to the signal input terminal, and the input signal voltage is clamped at a voltage equal to the reference voltage. When the switch circuit comprises a CMOS transfer gate, a voltage drop does not occur across the switch circuit regardless of the value of the bias voltage.

In a charge transfer device, the threshold voltage of a drive MOS transistor in an output circuit is set to be largest among those of MOS transistors of the same conductivity type which are formed on a substrate. Even under a large reset pulse, the MOS transistor is operable in a saturation region, because its threshold voltage is set to be large.

Charge transfer device

In a charge transfer device, a voltage generating cirucit generates a voltage amounting to a potential lower by '.alpha.' (.alpha.: a predetermined potential) than a potential formed under a reset gate electrode when stored charges of a floating diffusion region are discharged into a drain region. A voltage step-up circuit steps up a predetermined voltage and supplies the stepped-up voltage as a reset voltage to the drain region. A comparison/control circuit generates an error voltage amounting to a difference between the output voltage of the voltage generating circuit and the stepped-up voltage, and controls the voltage step-up operation by the step-up circuit according to the error voltage. With the structure of the device, the stepped-up voltage from the voltage step-up circuit, which is supplied as a reset voltage to the drain region, is controlled according to the process parameter variations. The result is that the reset voltage well follows up the process parameter variations, the dynamic range of the output signal is always kept wide, and the output signal of good linearity and good S/N performance can be obtained.

Charge transfer device with reset voltage generating circuit

A floating diffusion region and a drain region are formed separately from each other in a substrate. A reset electrode is arranged above an area located between the drain region and the floating diffusion region. A voltage step-up circuit having a reference voltage generator receiving a power source voltage for generating a reference voltage and a step-up circuit receiving a clock pulse for applying a voltage level of the clock pulse to the reference voltage applies a voltage to the drain region. The gate of a conversion E type MOS transistor for converting and outputting the charge stored in the floating diffusion region to a signal having a voltage level proportional to the charge amount is connected to the floating diffusion region. The reference voltage generator has D type MOS transistor and E type MOS transistor connected in cascade for producing the reference voltage of the value corresponding to the variation from a process center of the manufacturing process of this charge transfer device. The D type MOS transsitor has the same conductivity type and construction as the MOS transistor formed of the reset electrode, the floating diffusion region and the drain region. The E type MOS transistor has the same conductivity type as the conversion E type MOS transistor.

Charge transfer device with booster circuit

A charge transfer device includes a source barrier electrode arranged on portion of an insulation film which lies between a source region and a signal input electrode over a semiconductor substrate and formed to isolate the source region from the signal input electrode, and a source storing electrode for storing substantial source charge. A pulse signal is supplied to the source barrier electrode and source storing electrode, and a D.C. source voltage is applied to the source region.

Input circuit of charge transfer device

In a semiconductor circuit including a wave shaper circuit and a driver circuit, the wave shaper circuit is supplied with the reference potential via a wiring, which is provided independent of a wiring for supplying the reference potential to a driver circuit. With this feature, a variation in the potential of the wiring for supplying the reference potential to the wave shaper circuit is minimized.

Semiconductor circuit for driving a load circuit with power supplied

This device comprises transfer electrodes and read electrodes. The read electrode operates in accordance with two modes. Where it operates based on the charge detection mode, a charge below the read electrode is read out in accordance with the floating gate system, so that a charge detection signal is produced. On the other hand, where it operates based on the charge transfer mode, the read electrode performs a function equivalent to the transfer electrode. This device further comprises selector means, thus permitting the read electrode to select either of two modes to operate in a selected mode.

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Yokohama, Japan

Shin-ichi Imai