Samsung Electronics Co., Ltd.

Hyundai Electronics Industries Co. Ltd.

Shin-Dug Kim

Tack-don Han

Jung-Hoon Lee

Kyoung-woo Lee

Gi-ho Park

Seh-woong Jeong

Sang-hyun Park

Hye-Jeong Nam

Suk Kyu Chang

Nam-Kyu Lee

Sung-Bong Yang

A method is provided for controlling a cache system. The cache system to be controlled comprises a direct-mapped cache configured with a small block size, and a fully associative spatial buffer configured with a large block, which includes a plurality of small blocks. Where accesses to the direct-mapped cache and the fully associative buffer are misses, data of a missed address and data of adjacent addresses are copied to the large block in the fully associative spatial buffer according to a first-in-first-out (FIFO) process. Furthermore, if one or more small data blocks is accessed among its corresponding large block of data which is to be expelled from the fully associative buffer, the small block(s) accessed is copied to the direct-mapped cache.

Cache system and method for controlling the cache system comprising direct-mapped cache and fully-associative buffer

A translation look-aside buffer (TLB) capable of reducing power consumption and improving performance of a memory is provided. The fully-associative TLB which converts a virtual address into a physical address, comprises a first TLB having a plurality of banks; a second TLB having a plurality of entries, each of which having one virtual page number and 2physical page numbers, wherein N is a natural number; and a selection circuit for outputting an output signal of the first TLB to the second TLB in response to a selection signal, wherein each bank of the first TLB has a plurality of entries, each of which has one virtual page number and one physical page number. The size of a page indicated by a virtual page number of the first TLB is different from the size of a page indicated by a virtual page number of the second TLB.

Translation look-aside buffer for improving performance and reducing power consumption of a memory and memory management method using the same

A method of and a circuit for instruction/data prefetching using a non-referenced prefetch cache, adapted to store instruction/data blocks prefetched in accordance with a variety of existing prefetchinig machanisms, but not referenced by the central processing unit in an on-chip memory as the non-referenced prefetch cache without discarding them when they are replaced by new ones in a prefetch buffer so that a direct memory reference to the non-referenced prefetch instruction/data blocks can be achieved when they are to be referenced at later times, without any requirement of fetching or prefetching them from the lower memory again. Accordingly, it is possible to not only decrease the number of cache misses and the memory latency due to the fetching of instructions/data from the lower memory for the reference to the instructions/data, but also to reduce memory traffic.

Method of and circuit for instruction/data prefetching using non-referenced prefetch cache

A method for storing parity and rebuilding the data contents of two failed disks in an external storage subsystem comprises the steps of: proving a disk array defined as a matrix of (N-1).sup.* N including N disks each logically divided into N-1 data blocks where N is a prime number, the data blocks of a row being defined as a horizontal parity group, the data blocks existing in a rightwardly and upwardly continuous diagonal line being defined as a diagonal parity group; defining the data blocks existing in the diagonal line leftwardly and downwardly from the first data block of the (N-1) disk to the last data block of the first disk as horizontal parity blocks; defining the data blocks existing in the (N-1) row of the matrix as diagonal parity blocks; exclusive OR'ing (XORing) the contents of each of the horizontal and diagonal parity groups to obtain the parity value stored into the parity block of the corresponding horizontal or diagonal parity group; and analyzing a diagonal parity group including an error data block of the two failed disks to restore the error data block and then, the horizontal parity group including the restored error data block to restore another error data block, wherein the last analyzing step is repeated to completely rebuild the data contents of the two failed disks.

Method for storing parity and rebuilding data contents of failed disks

A disk drive constructed according to an exemplary embodiment of the present invention includes a disk having a plurality of tracks formed concentrically along a first surface of the disk for storing data. The tracks are divided into first and second data storage regions positioned between an innermost circumferential region and an outermost circumferential region of the disk. First and second heads write and read data to and from the first surface of the disk. The first head is positioned to access the first data storage region while the second head is positioned to access the second data storage region, and the first head being positioned to access the second data storage region while the second head is positioned to access the first data storage region. First and second arm assemblies are respectively connected to the first and second heads. The first arm assembly extends the first head over a first radius of the disk, and the second arm assembly extends the second head over a second radius of the disk. An actuator shifts the first and second heads among the tracks by driving the first and second arm assemblies. A control unit enables selection of the one of the first and second heads that is closer to a target position on the first surface of the disk so that the closer head can access the data at the target track.

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Goyang, South Korea

Shin-Dug Kim