Hynix Semiconductor Inc.

Skhynix Inc.

Shin-Deok Kang

Yong-Ju Kim

Hae-Rang Choi

Jae-Min Jang

Ji-Wang Lee

Dae-Han Kwon

Jong-Tae Kwak

Dong-Uk Lee

Ki-Chang Kwean

Ja-Seung Gou

A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

Clock generation circuit

A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

Duty cycle correction circuit and operation method thereof

A filter circuit includes a filtering unit configured to filter an input signal and generate an output signal, and a weight generation unit configured to monitor a variation of the output signal and generate weight information based on the monitored variation.

Filter circuit, integrated circuit including the same, and signal filtering method

An integrated circuit includes a counter configured to perform a counting operation and output a count code value. The integrated circuit further includes an operation controller, a digital circuit and an alignment unit. The operation controller receives the count code value and generates a first control signal and a second control signal. The first control signal is generated, when the count code value is equal to a first value, which is counted by the counter prior to a target count value. The second control signal is generated, when the count code value is equal to the target count value. A digital circuit performs a first operation based on the first control signal, and output a digital signal. An alignment unit aligns the digital signal, and outputs the aligned digital signal as a final digital signal in response to the second control signal.

Integrated circuit and method for driving the same

A semiconductor integrated circuit can include a reference voltage pad that can be configured to receive an external reference voltage and supply the external reference voltage to the inside of the semiconductor integrated circuit, an internal reference voltage generator that can be configured to generate an internal reference voltage by voltage dividing, a selector that can be configured to select and output one of the external reference voltage and the internal reference voltage in response to a selection signal, and a voltage trimming block that can be configured to regulate the level of the output voltage from the selector in response to trimming signals and outputs the level-regulated voltage as a reference voltage.

Semiconductor integrated circuit having level regulation for reference voltage

An input circuit for a semiconductor integrated circuit in which an operational state is constant even when a process condition, a temperature, a voltage, and the like are varied at the time of operation is provided. The input circuit includes a first input unit that performs a first amplifying operation on a potential difference between a reference voltage and an input signal and outputs a result of the amplification, and a second input unit that performs a second amplifying operation on a signal amplified by the first input unit and outputs a result of the amplification.

Input circuit for semiconductor integrated circuit

A test circuit includes an output control section for generating a plurality of output buffer control signals in response to a plurality of data masking signals when a test mode signal is activated in read operation; and a data output buffer for masking some of data input and output pins in response to the plurality of output buffer control signals.

Test circuit for a semiconductor integrated circuit

A refresh control circuit for use in a semiconductor memory device having a plurality of banks, including: a bank number signal generator for generating a plurality of bank number signals having a predetermined delay time between generation timings of the plurality of bank number signals based on a refresh signal and a reference signal; and a bank selection unit for generating a plurality of bank selection signals in response to the plurality of bank number signals and a piled-refresh control signals to thereby refresh the plurality of banks.

Refresh control circuit and method for multi-bank structure DRAM

A synchronous memory device can reduce unnecessary current consumption in its operation. In the synchronous memory device, a clock receiver receives an external clock to output a first internal clock. An address latch unit receives and latches an address in synchronous with the first internal clock. A row address latch unit latches a row address that is outputted from the address latch unit. A column address control unit receives the first internal clock to output a second internal clock and stops the output of the second internal clock when a non-column command is performed. Finally, a column address control unit is activated in response to the second internal clock to count a column address that is outputted from the address latch unit so as to output an inner column address.

Growing community of inventors

Gyeonggi-do, South Korea

Shin-Deok Kang