Texas Instruments Corporation

Exar Corporation

Shin Chung Chen

Fulvio Spagna

Roubik Gregorian

Mir Bahram Ghaderi

Vincent S Tso

Vincent Wing Sing Tso

A mechanism for dealing with faster clock speeds by increasing the pulse width of the pump-up and pump-down pulses of a Hogge-type phase detector without dividing the clock. In particular, the NRZ data stream is divided into two, interleaved data streams which are provided through two series of flip-flops. By connecting the exclusive-OR gates separately to the two series of flip-flops to generate the pump-up and pump-down pulses, a longer time between transitions can be achieved by having alternate transitions (up and down) used by the two different series of flip-flops. In addition, delay circuits are provided to compensate for the clock-to-data output delay of the flip-flops.

Interleaved pulse-extended phase detector

A charge pump circuit with a small loop filter capacitor is disclosed in the invention. This is accomplished by providing multiple currents which add to the desired current, I. A switching circuit switches one of the currents through the capacitor, while directing a combination of the multiple currents through the resistors. In this way, a smaller current is provided through the capacitor, allowing the capacitor to be much smaller in size.

Loop filter capacitor multiplication in a charge pump circuit

A phase selector circuit for the interpolation of phase signals including a state machine for outputting data in accordance with a clock signal and a logic circuit for receiving said output data from said state machine, the logic circuit causing a clock-to-data delay for data falling longer than a clock-to-data delay for data rising.

Simple glitchless phase selection method for multiplexing the phase interpolated clocks

The present invention provides a method and apparatus for half symbol delay calibration for phase window centering. To perform calibration of phase window centering, a carefully designed input signal is applied to the data signal input of a phase detector and a corresponding gating signal is applied to each of two D flip-flops. A calibration circuit produces the gating signal to enable the D flip-flops and the complement of the gating signal to temporarily prevent disturbance of a charge pump. In the preferred embodiment of the present invention, the calibration circuit provides a divide-by-4 clock function. The carefully designed input signal used for calibration includes on-time pulses and time-shifted pulses. The on-time pulses have rising edges that rise with the rising edges of the VCO clock signal. The time-shifted pulses follow the on-time pulses by 2.5 clock cycles of the VCO clock signal. If the half symbol delay is optimized, the phase detector will be equally likely to produce a pump up or a pump down signal. If the time-shifted pulses occur early or late relative to the rising edges of the VCO clock signal, then there will be more pump up or more pump down signals respectively. This information is used to calibrate the half symbol delay.

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Los Gatos, CA, United States of America

Shin Chung Chen